Ayush Jain — Director of Engineering
Specialties: Programming and Software skills: • Languages:System Verilog, VerilogHDL , C/C++ , Assembly Language • Verification Methodologies : UVM , VMM • Verification Tools : Cadence , Questa , Axiom • Scripting: Perl • Cadence Design Tools: Virtuoso • Design Tools: Calibre-Layout, DRC, LVS, PEX • Synopsys Design Tools: HSpice, Design Vision • Other Software: MATLAB, CCStudio,T- spice • Processors: ARM Cortex 8A
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI verification.
Location: Hyderabad, Telangana, India
Experience: 15 yrs 7 mos
Skills
- Functional Verification
- Asic
Career Highlights
- Expert in ASIC and VLSI design methodologies.
- Proficient in UVM and System Verilog for verification.
- Strong background in semiconductor industry roles.
Work Experience
AMD
Manager Silicon Design Engineering (1 yr 10 mos)
MTS( Member of Technical Staff) Silicon Design Engineer (2 yrs)
Senior Silicon Design Engineer (5 mos)
Xilinx
Senior Design Verification Engineer 2 (2 yrs 6 mos)
Senior Design Verification Engineer 1 (2 yrs 10 mos)
Qualcomm
Engineer (1 yr 11 mos)
Cortina Systems
ASIC Design Verification Engineer (2 yrs 4 mos)
North Carolina State University
Student (1 yr 9 mos)
University of Paris
Internship Trainee (3 mos)
Indian Institute of Technology, Delhi
Project Trainee (5 mos)
Education
MS at North Carolina State University
B.Tech at Vellore Institute of Technology
at BVM
