Rahul Vyas

Software Engineer

The Hague, South Holland, Netherlands7 yrs 11 mos experience

Key Highlights

Expert in System on Chip and FPGA design.
Experience in Quantum Computing and Aerospace industries.
Proven track record in low latency and high performance computing.

Stackforce AI infers this person is a specialist in Quantum Computing and Aerospace with a focus on high-performance embedded systems.

Contact

Skills

Core Skills

System On Chip (soc)FpgaLow Latency DesignVhdlDigital Signal ProcessingSystem On A Chip (soc)Image Processing

Other Skills

ARM Cortex-M3ArduinoAtmel AVRC++CUDACommunication ProtocolsComputer ArchitectureDigital ElectronicsEmbedded CEmbedded Software ProgrammingEmbedded SystemsFPGA prototypingField-Programmable Gate Arrays (FPGA)GitHigh-speed Digital Design

About

I am Computer Engineering professional with experience in System on chip (SoC) / FPGA, low latency, high performance computing & interface design and Embedded hardware-software co-design in fields like Quantum Computing, Aerospace, Medical instruments, video processing, internet of things, optics and RF Communication.

Experience

Fortaegis technologies

SoC-ASIC/FPGA Engineer

Mar 2024 – Present · 2 yrs · Amsterdam Area · On-site

System on chip (SoC) design (FPGA/ASIC) for ultra secure semiconductors for collaborative intelligent systems.

System on chip (SoC)FPGALow Latency Design

Qblox

Digital Design Engineer - Quantum Computing

Apr 2021 – Mar 2024 · 2 yrs 11 mos · Delft, South Holland, Netherlands

Design and maintenance of low latency digital systems for controlling quantum computers.
Full embedded stack development including custom processor, software defined radio (SDR), communication protocol and controller design on FPGA (SoC).
Linux device drivers and embedded software applications development to support higher level python based quantum-computing applications.
UVM based system verification, automation and development

VHDLUniversal Verification Methodology (UVM)TCLSystemVerilogC++Low Latency Design

Google summer of code

Google Summer of Code | Mentor | SoC-FPGA | Video Processing

May 2020 – Aug 2020 · 3 mos

Mentoring open source project related to FPGA based video processing accelerator design for Apertus organisation under Google Summer of code (GSOC-20) framework.
FPGA based Bidirectional Packet Protocol Design to support various bus protocols (like I2C, SPI..) over common LVDS link.

XILINX ZYNQVHDLImage ProcessingGitHigh-speed Digital DesignSystem on a Chip (SoC)

Hyperion technologies b.v.

2 roles

Digital Design Engineer - Aerospace/Satellite systems

Promoted

Oct 2019 – Mar 2021 · 1 yr 5 mos

FPGA based satellite systems design
Satellite LASER communication: DSP backend, High speed MODEM and on-board memory management system design.
UDP-IP based driver and controller design for multi channel deformable-mirror system.
Custom camera interface and linux device driver design for onboard computing Unit.

eMMCVHDLDigital Signal ProcessingC++Low-power DesignLinux Device Driver

Design Engineer

Oct 2018 – Sep 2019 · 11 mos

FPGA based satellite systems design
High speed Interface Design for onboard Computing Unit integration with the SpaceWire bus.

Cern

Intern

May 2019 – Jul 2019 · 2 mos · Geneva Area, Switzerland

Business Model development for technology patented by CERN (ATTRACT Project) in high precision vibration detection for optical satellite communication.

Scinvivo b.v.

Digital Design Engineer - Medical Imaging

Jul 2018 – Jul 2018 · 0 mo · Amsterdam Area, Netherlands

System on Chip (FPGA, CPU) design for optical MEMS based medical device.
Mainly involved in the synchronization of drive electronics of the Scinvivo catheter with external OCT engine.

Google summer of code

Google Summer of Code | Developer | SoC-FPGA | Video Processing

May 2018 – Aug 2018 · 3 mos · Vienna, Vienna, Austria

Worked on designing image processing pipeline on XILINX ZYNQ -SoC for implementing realtime focus peaking. (Apertus- AXIOM)
VHDL based kernel design for hardware acceleration of Image Debayering and Focus Peaking algorithms
Design HW/SW architecture and video System integration

Cnrs

Digital design Engineer - RF/IoT

Jan 2016 – Aug 2017 · 1 yr 7 mos · Lille Area, France

Developed Reconfigurable Platform for Multi-Protocol Internet of Things Applications.
Worked with the National Instruments RIO (FPGA) and USRP (SDR) environment for developing Multi-standard gateway. The testbed supported technologies like LoRa, Bluetooth and Zigbee to connect with different sensors in a heterogenous WSN environment.
The testbed enables researchers to experiment with different wireless technologies as well as sensors for various internet of things based applications.
Worked on creating base band pipeline on reconfigurable platform (Xilinx ZYNQ- SoC) as a part of 5G testbed.

Inria

Research Intern (Internet of Things)

May 2015 – Jul 2015 · 2 mos · Lille Area, France

Experimental evaluation of the impact of interference on energy consumption in Wireless Sensor Networks.
Developed an Embedded Platform (Hardware and software) for the Measurement and Analysis of the performance of WSN Nodes in various environments with main focus on the analyses of the global energy consumed during interference.
Developed a probabilistic model to predict the battery life of the node at different interference conditions.
Proposed a low power solution for the Wireless Sensor Networks (Based on the experimental results).

Wesee, ministry of defense, govt. of india

Intern - FPGA (Avionics Systems) | ARINC-429

May 2014 – Jul 2014 · 2 mos · New Delhi Area, India

Developed FPGA based mixed signal embedded platform that acts as an interface between RS-232 Interface of Avionics -units with ARINC-429 Bus (Avionics Bus Communication Protocol).