Vandana Singh

Software Engineer

Bengaluru, Karnataka, India13 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in FPGA design and verification.
Proficient in RTL design and synthesis.
Strong project management skills in technical environments.

Stackforce AI infers this person is a Telecommunications FPGA Design Engineer with expertise in RTL and verification processes.

Contact

Skills

Core Skills

Fpga DesignRtl Design

Other Skills

AwkCDesign SimulationEthernetFPGA Modeling and VerificationFPGA RegressionsFPGA prototypingField-Programmable Gate Arrays (FPGA)Formal VerificationFunctional IntegrationLinuxLogic SynthesisOn-Chip DebuggingPerlPython

About

-- FPGA Design, Specification, and Micro-architecture -- RTL Design and Synthesis -- Simulation/Verification Using Verilog -- FPGA Prototyping, Static Timing Analysis, Design and Timing Constraints -- Verilog, TCL, Makefiles, Bash, Python and PERL Scripting -- Project Management using Excel, SVN, Wiki, and Design & Programming Document

Experience

Amd

MTS Silicon Design Engineer

Mar 2022 – Present · 4 yrs · Bengaluru, Karnataka, India

Intel corporation

Engineer

Oct 2016 – Feb 2022 · 5 yrs 4 mos

Tejas networks

Senior Engineer - R&D

Aug 2012 – Oct 2016 · 4 yrs 2 mos · Bangaluru

Projects:
GPON
Ethernet Mapping over PTN/OTN
FPGA Modeling and Verification
Work:
Ethernet over Optical Transport Network
RTL Coding, Functional Integration, Design Simulation, FPGA Regressions
Design Prototyping on FPGAs, Static Timing Analysis, Target Validation, On-Chip Debugging
Ethernet PCS/PMA, Gigabit Interface Validation
Tools Used:
Cadence IES and Aldec Riviera PRO for Simulation
Synopsys Synplify PRO was used for FPGA Synthesis
Quartus and Vivado for FPGA Designing