Vinay Kumar

Associate Consultant

Noida, Uttar Pradesh, India10 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in High Level Synthesis tools.
Proficient in RTL design and verification.
Strong experience in FPGA prototyping and debugging.

Stackforce AI infers this person is a specialist in FPGA design and verification within the semiconductor industry.

Contact

Skills

Core Skills

Rtl CodingFpga PrototypingCatapult HlsHigh Level SynthesisHardware EmulationRtl DesignSdsoc

Other Skills

AMBA AHBAltera QuartusCMOS designConfluenceDebuggingEmulatorFPGAField-Programmable Gate Arrays (FPGA)FormalProHDL DesignerHVDCIntel HLSIntel Quartus PrimeJIRALogic Synthesis

About

 Responsible for working on High Level Synthesis Tools like Catapult HLS and Vivado HLS. - Responsible for multiple language feature support in latest release of Precision RTL - Responsible for proof of concept studies for the integration of Catapult HLS (High level synthesis), FromalPro (Formal Verification), PowerPro (Power estimation and optimization) with Precision to improve quality of results and verification of generated RTLs for FPGA synthesis. Proficient with RTL design (Verilog coding) , System Verilog and Timing closure (STA)

Experience

10 yrs 11 mos

Total Experience

2 yrs 8 mos

Average Tenure

7 yrs 4 mos

Current Experience

Siemens eda (siemens digital industries software)

3 roles

Member of Consulting Staff

Jan 2024 – Present · 2 yrs 3 mos · Noida, Uttar Pradesh, India · On-site

RTL CodingVerilog HDLLogic SynthesisPrecision SynthesisFPGA prototypingField-Programmable Gate Arrays (FPGA)+14

Lead Member Technical Staff

Jan 2021 – Dec 2023 · 2 yrs 11 mos · Noida, Uttar Pradesh, India · On-site

CATAPULT HLSFPGA prototypingVerilog HDLHardware EmulationEmulatorAMBA AHB

Senior Member of Technical Staff

Nov 2017 – Jan 2020 · 2 yrs 2 mos · Noida, Uttar Pradesh, India · On-site

Responsible for working on High Level Synthesis Tools like ASIC Catapult HLS and Vivado HLS.
Responsible for multiple language feature support in latest release of Precision RTL
Responsible for proof of concept studies for the integration of Catapult HLS (High level synthesis), FromalPro (Formal Verification), PowerPro (Power estimation and optimization) with Precision to improve quality of results and verification of generated RTLs for FPGA synthesis.
Test a software utility to generate DSP intensive RTLs to test and benchmark Precision RTL (logic synthesis tool) for inferring DSP in FPGA
Ensured functional and behavioral characteristics of Precision RTL by running multiple customer design to expose the tool to new user scenarios
Tested multiple features of Precision RTL including high reliability triple modular redundancy(TMR), incremental synthesis, retiming, compile for time, compile for area etc

CATAPULT HLSAltera QuartusField-Programmable Gate Arrays (FPGA)DebuggingFormalProHigh Level Synthesis+15

Ge

Software Control Engineer

Jun 2017 – Jul 2017 · 1 mo · Stafford, Staffordshire, United Kingdom

 Responsible for designing RTL code (Verilog HDL), Test Stimulus, IO Pin Planning, Testing or validation, synthesis, Implementation on FPGA Platform using Xilinx Vivado/ISE
 Real time FPGA Debugging /testing using Xilinx ILA IP Core (Logic Analyzer), which is in build IP available in Xilinx Vivado
 Knowledge of Dual Core ARM Cortex A9 is Physically available in Zynq 7000 architecture and which is integrated with Xilinx FPGA Chips
 Writing Test harness i.e Testbench for the verification of RTL Design, some time using TCL language to automate our design or test, Vivado is a tcl friendly
 Learning System Architect Language (SAL) GE’s propriety language which useful for interfacing of Series V hardware which contains FPGA ICs, Intel i7 (Kontron) Processor.

HVDCPower SystemsFPGA prototypingField-Programmable Gate Arrays (FPGA)Hardware EmulationEmulator+1

Ge renewable energy

Software Control Engineer

May 2016 – Oct 2017 · 1 yr 5 mos · Noida Area, India · On-site

 Responsible for designing RTL code (Verilog HDL), Test Stimulus, IO Pin Planning, Testing or validation, synthesis, Implementation on FPGA Platform using Xilinx Vivado/ISE
 Real time FPGA Debugging /testing using Xilinx ILA IP Core (Logic Analyzer), which is in build IP available in Xilinx Vivado
 Knowledge of Dual Core ARM Cortex A9 is Physically available in Zynq 7000 architecture and which is integrated with Xilinx FPGA Chips
 Writing Test harness i.e Testbench for the verification of RTL Design, some time using TCL language to automate our design or test, Vivado is a tcl friendly
 Learning System Architect Language (SAL) GE’s propriety language which useful for interfacing of Series V hardware which contains FPGA ICs, Intel i7 (Kontron) Processor.
 Responsible for designing RTL code (Verilog HDL), Test Stimulus, IO Pin Planning, Testing or validation, synthesis, Implementation on FPGA Platform using Xilinx Vivado/ISE
 Real time FPGA Debugging /testing using Xilinx ILA IP Core (Logic Analyzer), which is in build IP available in Xilinx Vivado
 Knowledge of Dual Core ARM Cortex A9 is Physically available in Zynq 7000 architecture and which is integrated with Xilinx FPGA Chips
 Writing Test harness i.e Testbench for the verification of RTL Design, some time using TCL language to automate our design or test, Vivado is a tcl friendly
 Learning System Architect Language (SAL) GE’s propriety language which useful for interfacing of Series V hardware which contains FPGA ICs, Intel i7 (Kontron) Processor.

HVDCPower SystemsFPGA prototypingField-Programmable Gate Arrays (FPGA)Hardware EmulationEmulator+1

Coreel technologies (i) pvt. ltd

Application Engineer | EDA

Oct 2014 – Apr 2016 · 1 yr 6 mos · Greater Delhi Area

> Provided technical applications engineering support directly to customers.
> Experience in Analysis, troubleshooting, debugging and resolving the issues in timely manner.
> Provided design solutions for Place and Route, Timing Closure, Simulation and synthesis to
Proficient in preparing Defect logs and tracking defects to closure.
> Worked SDSoC Platform which is stands for Software Define SoC.
> Xilinx has introduced SDSoC, a new C/C++ development environment. The third member of the
Xilinx SDx family of development environments.
1. Environment provides a simplified like C/C++ programming experience.
2. Full system level profiling, automated software acceleration in programmable logic
3. It simplifies the process of identifying and accelerating functions.
> Write C based coding and SDSoC will generate block diagram (Block Design- can see on Vivado IPI) and you can open that in Vivado IPI and SDSoc.
> Xilinx Tools:
 Vivado 2015.1
 Vivado 2014.4
 ISE 14.7,
 Plan Ahead , SDSoC , MPSoC
 Logic Analyzer,
 ChipScope Pro ,
 Vivado HLS ,
 Vivado SDK, etc..
> FPGA Board:
 Zynq 7000 ApSoC -
 Zedboard ,
ZC702
 Zybo ,
 Artix -7
VC709 Vertex 7,
 Nexys 4 DDR ,
 Nexys 4 Video ,
 FMC Cards ,
 Digilent analog discovery kit , etc..
> Mentor Graphics EDA Tools:
 Model Sim
 Questa Sim
 HDL Designer ,
 Precision RTL Synthesis (Uses for FPGA based design)

Dkop labs pvt. ltd

Design Engineer - Intern

Jan 2014 – Sep 2014 · 8 mos · Noida, Uttar Pradesh, India

>Got Hands on practice topics like VLSI Design Flow , RTL Design ,FPGA , Linux , TLC/TK,
System Verilog , Questa Sim.
> Worked on Various EDA Tools like ModelSim/QuestaSim for design & Verification , PSIPCE ,
XILINX ISE , Mentor Graphics Pyxis IC Station , Calibre etc.
> Worked as a trainer in the DKOP Labs itself .
> Taken labs and Taught Verilog, Xilinx ISE FPGA Flow ,and ChipScope Pro.
Worked on Various Projects Like:
1. Adaptive Filter Using Verilog and Synthesis on FPGA .
2. FIFO
3. SPI protocol
4. I2C protocol