Navathej Bangari

Software Engineer

Bengaluru, Karnataka, India10 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in System Verilog and UVM methodologies.
Proficient in digital and analog circuit design.
Experienced in memory modeling and validation.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI and digital design.

Contact

Skills

Core Skills

Functional VerificationDigital DesignMemory Modeling

Other Skills

ASICAdvanced memory validationCCMOSCSI-Phy integration VerificationDigital DesignsGate Level SimulationIntegrated Circuit DesignPerlPower ManagementPower aware SimulationRTL DESIGNRTL DesignSemiconductorsTCL

About

•Experience in testbench/testcase coding using System Verilog/Verilog for block level and also Chip level Verification. •Good understanding of System Verilog, latest verification methodology UVM and System Verilog Assertion. •Knowledge of Constrained-Random test cases, Coverage Driven verification. •Knowledge on how to develop Driver, Generator, Monitor and Scoreboard using system Verilog and UVM. •Good understanding of MOS Transistor, CMOS process (Fabrication), Digital design and Analog Circuits. Specialties: verilog, system verilog, logic design, uvm,

Experience

Ampere

2 roles

Staff Verification Engineer

Feb 2021 – Present · 5 yrs 1 mo

Senior Verification Engineer

Feb 2019 – Feb 2021 · 2 yrs

Aricent

Design and Verification Engineer

Jun 2017 – Feb 2019 · 1 yr 8 mos · Bengaluru Area, India

worked at Qualcomm as camera sub system verification Engineer.
Responsibilities:
Gate Level Simulation
Power aware Simulation
CSI-Phy integration Verification

Gate Level SimulationPower aware SimulationCSI-Phy integration VerificationFunctional VerificationDigital Design

Zia semiconductor pvt ltd

Design Engineer-Memory Modeling

Feb 2015 – Jan 2017 · 1 yr 11 mos · Noida Area, India

worked at ST Microelectronics,Greater Noida as Memory Modeling engineer (as a subcon through zia semiconductor)
Responsibilities:
Responsible for Developing and verifying of verilog functional view and verilog timing view for different flavors of RAMs and ROMs.
Responsible for Developing Synopsis Liberty file (which contains timing,power and leakage information)
Responsible for Advanced memory validation of Dft/test views such as Tetramax ,Fastscan and CTL.

VerilogFunctional VerificationMemory ModelingAdvanced memory validation