Madhusudhana Reddy — CEO

19 years of firsthand experience in Systems and Architecture , RTL design and SoC / Subsystem /Core verification with expertise in power aware verification, power estimation, GLS and test vector development. Managing large teams and delivering complex first time design and DV deliverables. Part of IEEE 1801 UPF standard development • Infra Systems and Architect - LPDDR , NOC, Access Control . uARCH development of IO Subsystems (PCIE) for Data Center Type of applications . RTL design and microarchitectural Activities of security and Power controller. . Low Power Methodology Lead to drive various low power verification activities across QCOM • Experience in creating Architecture model using PSS standard and auto generating System tests for verification • Verification Lead for Complex Sub Systems and Cores • Low Power DV Activities for multiple SoC’s. • Low Power DV flow with Formal Engines • Experience in Creating test plans, Coding test cases, assertions, creating test bench using System Verilog and OVM, UVM verification methodology. • Expert in functional & Low Power verification, debugging RTL and gate level Netlist simulations • Experience in generating Power Vectors for PTPX. • Participated in Validation Activities and ATE debug for multiple SoC’s. • Experience in managing large teams and delivering multiple projects Technical Skills: • Bus Protocols: LPDDR, PCIE, AHB, AXI, SPI, I2C, SDRAM, DSI, CSI, PCIE, MIPI D-Phy and C-Phy • Linting Tools : PLDRC • Power Estimation Tools: PTPX • Low Power Tools: VCS-NLP, MVSIM, MVRC • HDL: Verilog, System Verilog, SVA • Verification Environment: UVM • Simulation Tools: VCS, Questa • Software language: C • Scripting Language: Perl • Debugging Tools: Verdi, Simvision, DVE • Version control software: Clear-case, IDM, Perforce.

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in power-aware design and architecture.

Location: Bengaluru, Karnataka, India

Experience: 19 yrs 9 mos