Sep 2018 – Jun 2020 · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

• 1. Networking SoC: Built functional hardware emulation models of complex systems for hardware and software development teams, Created emulation/FPGA models from RTL design using emulation/FPGA synthesis, partitioning and routing tools, model build flows develop & maintain, developed hardware collateral to be integrated with the Emulation model, Developed direct & constrained-random stimulus,
• 2. SoC Implementation responsibility from RTL-to-gds for customer design in Finfet process: Responsible for team delivery of Blocks & Subsystems implementation, Synthesis, Placement, timing reviews, STA, timing closure ECOs & customer feedback on timing, congestion, violation fixing & signoff
• 3. RISC Processor Verification: Responsible for Test Plan, Tests debug & Team leadership for verification of different IPs for Processor+Cache Subsystem for European Client
• Owner for Verification & support to FPGA team for Emulation. Debugged & fixed Emulation issues of design

Mar 2017 – Aug 2018 · 1 yr 5 mos · Noida Area, India

• 1. Emulation Lead for simulating Signal Processing Core on Synopsys Emulation platform taking help from Synopsys AEs & internal team of 3 emulation engrs. Lot of struggle in making the design work under very tight customer requirements and schedule.
• 2. Design Verification Manager for a digital networking design from Test plan definition at top level to devising verification strategy for 10+ IPs alongwith design debug & Gatelevel simulations cleanup. Involved regular interaction with RTL team & Emulation team for making the design work on FPGA emulator for client NXP.
• 3. SoC Implementation responsibility from RTL-to-gds for ~200mm2 design 16nm Finfet process: Major Blocks & Supers implementation, QoR reviews, STA, timing closure ECOs & customer feedback on timing, congestion, violation fixing & signoff, Design Verification at SoC level & main IPs: execution and customer interaction.
• 3. SoC Implentation responsibility from Netlist-to-gds for ~15mm2 design 28nm process: Involved responsibility of Physical Design Implementation, STA closure, execution & Reviews internally and with customer.
• 4. Project Management of Physical Design, DFT, Design Verification & Emulation activities for Semiconductor Clients. Team Management, build and Milestone delivery project responsibility.

Nov 2011 – Mar 2017 · 5 yrs 4 mos · Noida Area, India

• IP/Memory Design
• 1. Memory Compiler design for 16nm Finfet node for a leading foundry: My contribution includes architecture review,design changes, characterization, validation and QA for a set of compilers alongwith managing a team handling this node.
• 2. Engineering: Memory & Memory compiler design for 28nm. Taiwan Customer
• For lowpower process 28HLP: Completed Three designs: Singleport HighSpeed, Dualport High density & ROM alongwith Testchip instances. Speed improvement & several enhancements achieved through design changes.
• 3. Memory compiler design for 14nm node: Involved in new flow setup & implementation using finfet node as reference.

Apr 2011 – Oct 2011 · 6 mos · Hyderabad Area, India

• Fusion (Processor+Graphics) Productline: Silicon Implementation
• Design/Layout for Microprocessor & Graphic Product line: Responsibility for Product Implementation from RTL to gds, STA, Timing Closure & Silicon support. The design was in 28nm, 218mm2, partitioned into various subblocks which are implemented & closed standalone. Critical blocks done were Ethernet IP with PHY, DDR with its specialized IOs (mixed signal) and PHY & digital compute arrays(datapaths).

Jul 2010 – Mar 2011 · 8 mos · Pune Area, India

• DDR PHY: Design & layout, Customer deliveries
• 1. DDR Design(CORE): Responsible for RTL refinement, synthesis, Timing analysis, physical layout & functional verification (RTL,GLS) for customer specific IP requests. Team size: 10 engrs. As per customer requirements, the configurable RTL is generated, verified & delivered as combination of carefully balanced hard macros for ctrl & data bits alongwith soft logic.
• 2. DDR Design(PHY): Setup backend flow using ICC (earlier SOCE in VIRL). 1 to 2 hard macros are delivered by me settingup the flow in any process technology, remaining by the team. RTL & Gatelevel simulations are performed for functional verification which are very exhaustive. Lead for 28nm TSMC process DDR3-1600 design with new proprietary features both for customer and testchip.

Oct 2009 – Jul 2010 · 9 mos · Ahmedabad Area, India

• Design & Implementation of Customer SoC in 65nm
• Responsible for execution of design projects (FPGA, ASIC, SoC & IP) as per Customer requests. Team size varies from 2-12 engineers per project. Interactions with customer for project scope, definition plan & execution. Frontface with Semiconductor customers. Project execution schedule & deliverables are defined by me. Also handled Presales support with Sales team in US & Europe.
• Worked on fullchip implementation for a digital video customer in US,Florida. My
• Scope includes RTL build, integration,DFT insertion , STA & physical implementation till PG in 65nm TSMC process.. This was 4 months project with PG done in July’10.
• Also, worked for top EDA vendors for design of their IPs. Scope involves RTL coding, netlist verification, constraints & timing analysis.

Feb 1996 – Sep 2009 · 13 yrs 7 mos · Noida Area, India

• 1. HVD Division SetTopBox Design Mgr : Design team consisted of Microarchitecture, frontend integration, PnR, verification & Product engg support (incl DFT) teams. My role was technical supervision with handson work on timing analysis & physical implementation closure.
• At Noida design centre successfully delivered STB 5188 (Sat 288 FE integrated with Omega backend ) chip which is ST’s first integrated solution for lowcost Retail STB market. Also delivered was STB5162 (362 FE demodulator integrated with MPEG2 Backend decoder): This was first time silicon success with Cut 1.1 moving to production. STB5197 Product was another product delivered in 2008 for the US cable market.
• 2. Worked on design of STB7105/6 in 55nm (HD decoder with SD display with H264 backend decoder for Airtel STB). My role involves project execution responsibility interacting with teams in Business Units to define specs for Silicon project, execute it in noida design center & also support product engg teams in Grenoble,France so as to deliver working silicon.
• 3. Designed STB 5211/97 STB exclusively for TataSKY : now in production. The design was in 65nm with complete implementation from DOS to PG was done by my team. The product is the highest selling STB for India market.
• 4. SetTopBox SoC projects include Design Management of following ST products : STm5589, STi5300, STv5107, STi5700, STB0299e.
• 5. DVD Division IP Mgr : Responsible for identifying needs of IPs across complete division in Noida, Italy & UK sites, their architecture definition, RTL implementation , Frontend checks, delivery to SoC teams for integration, Followup with silicon validation & characterization teams for bugs/fixes.
• This was first exposure to Consumer market. The IP evolution was very fast & roadmap quite bumpy. Example IPs: DDR Memory controller, Flash/RAM Memory Controller, ST20 host processor, Video blocks, display blocks, Audio decoders (pcm player, reader, spdif player)