Aug 2009 – May 2011 · 1 yr 9 mos

• I did my M. Tech in Microlectronics, VLSI and Display technology at IIT Kanpur.
• Dr. Bahniman Ghosh
• M.Tech Thesis:-Design of a High speed 12 bit flash ADC with the Optimization of power & area, A novel 1.8 V, 12 bit two-step Analog to digital converter (ADC) architecture based on the dichotomic anticipation algorithm. The proposed conversion algorithm is based on the dichotomic method with anticipation
• which increases the conversion speed of the converter and reduces the power consumption of the complete circuit.
• Term Projects:-
• 1]A Low Voltage Low Power Current Mirror OTA for Sigma-Delta Modulator implemented using IHP 180 nm CMOS standard process in cadence.
• 2]A low power divide-by-8 injection-locked fully differential frequency divider Implementation with TSMC 180nm technology using current- mode logic (CML) D-latches