SHASHI KANT ANAND

Director of Engineering

Bengaluru, Karnataka, India13 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 9 years of experience in semiconductor design.
Expertise in static timing analysis and physical design.
Proven track record in successful silicon timing closure.

Stackforce AI infers this person is a Semiconductor Design Expert with a focus on Timing Analysis and Physical Design.

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Skills

Core Skills

Embedded SystemsStatic Timing AnalysisPhysical Design

Other Skills

Tcl-TkPower AnalysisScriptingFormal VerificationDDR DesignVLSIDigital ElectronicsVerilogIntegrated Circuit DesignComputer ArchitectureLow-power DesignAnalogASICSoCVHDL

About

Classify, Concentrate and Create is my work style. I have strong passion of looking the problems in different way with an edge of doing something innovative. I always try hard to ease the problems and increase the efficiency with coordination of all the small big leanings that I have being as technical and non technical. I believe in clear vision and streamlined execution and enjoy the TEAM WORK... 9+ years of experience across various Semiconductor design domains and roles spanning Physical Design Synthesis , Front End Integration & STA timing signoff. Have accomplished various successful Silicon Timing closure on lower nodes. Technical expertise on designs including Graphics, DDR PHY, Modem & SoC. Current Role: Technical Lead in Mediatek for Design Integration & Timing Signoff for 5G Modem,

Experience

13 yrs 9 mos

Total Experience

4 yrs 7 mos

Average Tenure

8 yrs 10 mos

Current Experience

Mediatek

3 roles

Department Manager

Promoted

Aug 2024 – Present · 1 yr 9 mos

Technical Manager

Jan 2023 – Aug 2024 · 1 yr 7 mos

Tcl-TkEmbedded Systems

Senior Staff Engineer

Jul 2017 – Jun 2023 · 5 yrs 11 mos

Front End Integration of MODEM/WCD. STA/Synthesis & Signoff.

Cadence design systems

Senior Design Engineer

Jul 2015 – Aug 2017 · 2 yrs 1 mo · Bengaluru Area, India

Full Chip STA of DDR Test Chip, Slices PNR and timing closure, High Speed DDR3/4 LPDDR/Combo Designs

Amd

Physical Design Engineer

Jul 2012 – Jun 2015 · 2 yrs 11 mos · Bangalore India

++Key Responsibilities Handled:
+PD closure of AMD low power and complex processor blocks on lower technology nodes.
+Formal Verification of graphics blocks on full chip level.
+Blocks closure in tight ECO cycle.
++Expertise(Implementation):
+Floor Planning, Clock Understanding and Synthesis, Design Partitioning and data path/control logic analysis. (in ICC & Encounter tools)
+Placement, algorithms, do's and don't for better results. (ICC)
+Back End Low power techniques and implementation.(ICC/OpenAccess Based custom algorithms)
+PreRoute and Post Route Optimization techniques (ICC) @ key metrics Area/Speed/Power.
+Design for SI, techniques (custom and scripting based) to handle signal integrity issues in high speed and lower node designs. (ICC)
+Tips and Tricks to clean up the LVS and left over DRC/ERC in short time.(Calibre)
+Fluent in running AMD internal SUPRA flows for complete Physical Design.
++Expertise(Analysis):
+Static Timing Analysis of the design and constraints check (Prime time, PT SI/VX/GCA)
+Developed Timing ECOs with physical constraints (aware with physical aware ECOs, PT DMSA)
+Power Analysis of the PNR complete design (Prime Time PX with VCD approach)
+IR Drop/EM issues analysis (Apache Red Hawk)
+Logic Equivalence Checks using Conformal (LEC), I owned this for blocks and full chip.
+Static checks for power gated designs (MVRC/VSI)
++Scripting
+Would rate myself 8/10, doing Scripting with TCL/Perl to handle PD tasks!! Have background of programming in C/embedded C/C++ during various B.Tech/Masters projects.Love Coding ....
+Configured and automated the PD metrics in AMD Internal Flow using Perl.
+Fast hands on Unix related day to day stuffs (gvim/awk/Csh...)
++Ongoing RnD @CAD
+Understanding of Open Access (Si2, perl/python wrapper) and custom Algo Implementation for low power heuristics.
+Active Member of Si2 Forum
++Ongoing RnD @Design
+Power Grid Design methodology, MCMM...