J

Jagjeevan Kandukuri

Product Manager

San Jose, California, United States18 yrs 8 mos experience

Key Highlights

  • Expert in full chip verification for advanced memory technologies.
  • Proven track record in NVMe design verification consulting.
  • Strong background in Universal Verification Methodology and related tools.
Stackforce AI infers this person is a Semiconductor Verification Specialist with expertise in memory technologies.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)Nvm Express (nvme)

Other Skills

AMBA AHBASICCDDR4DDR5FPGAFunctional VerificationLPDDR5ModelSimPHYPython (Programming Language)RTL designSoCStatic Timing AnalysisSystemVerilog

About

My recent role as Senior Member of Technical Staff at Mirafra Technologies involves full chip verification for AMD-Xilinx DDR MC, leveraging my extensive knowledge in DDR5, LPDDR5 and NVMe. Previously, as a Manager at Capgemini, I consulted with Intel on NVMe Design Verification, helping team in Verification closure.

Experience

Mirafra technologies

Senior Member of Technical Staff

Jul 2023Present · 2 yrs 8 mos · United States · Hybrid

  • Consultant to AMD-Xilinx, DDR MC Full Chip Verification .
LPDDR5Universal Verification Methodology (UVM)CDDR5Python (Programming Language)NVM Express (NVMe)

Capgemini

Manager

Oct 2021Jun 2023 · 1 yr 8 mos · India · Hybrid

  • Consultant to Intel, NVMe Design Verification.
NVM Express (NVMe)SystemVerilogUniversal Verification Methodology (UVM)

Capgemini engineering

Senior Technical Team Lead

Jul 2021Oct 2021 · 3 mos · Telangana, India · Hybrid

  • Consultant to Intel, NVMe Design Verification.
NVM Express (NVMe)SystemVerilogUniversal Verification Methodology (UVM)

Altran

Technical Lead

Jul 2018Jun 2021 · 2 yrs 11 mos · India · Hybrid

  • Consultant to Intel, NVMe Design Verification.
NVM Express (NVMe)SystemVerilogUniversal Verification Methodology (UVM)

Xilinx

Sr. Hardware Development Engineer

Jan 2012Jun 2018 · 6 yrs 5 mos · Hyderabad Area, India

Universal Verification Methodology (UVM)DDR4PHY

Stellarip solutions private limited

Senior Verification Engineer

Aug 2011Jan 2012 · 5 mos · Hyderabad, Telangana, India · On-site

Smsilicon india private limited

Sr. Design Engineer

May 2011Aug 2011 · 3 mos · Hyderabad Area, India · On-site

Stellarip solutions private limited

Verification Engineer

Apr 2007Apr 2011 · 4 yrs · Hyderabad, Telangana, India · On-site

Education

Kakatiya University

Baby Sainik High School

SRM

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