Akshay Revankar

CTO

San Francisco, California, United States9 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in SoC performance and power analysis.
Significant contributions to design verification methodologies.
Led initiatives to enhance data management in academia.

Stackforce AI infers this person is a Semiconductor and Hardware Architecture specialist with a focus on performance optimization.

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Skills

Core Skills

Soc ArchitecturePerformance AnalysisFpga DesignPerformance OptimizationNetwork ArchitectureDigital DesignVerification

Other Skills

ArduinoCC++CSSCadence VirtuosoElectronicsEngineeringField-Programmable Gate Arrays (FPGA)HTMLJavaScriptLeadershipLinuxMatlabMySQLNetwork Administration

About

Currently working as an SoC Performance Architect with the Platform Architecture team at Apple, working on post-silicon performance and power analysis on a wide range of Apple products. I did my masters in MS in Electrical and Computer Engineering at Carnegie Mellon University, focusing on areas of Computer Architecture and system design. Before pursuing my masters, I worked as a Digital Design Engineer with Texas Instruments for 3 years, focusing on areas of design verification of various peripherals, SoC infrastructure components, memory controllers, and radio controllers, and contributed significantly to new flow automation for faster device-to-device turnaround time.

Experience

Apple

SoC Platform Architecture

Jan 2023 – Present · 3 yrs 2 mos · Cupertino, California, United States · On-site

> Effectively lead cross-functional technical efforts in areas like cache policy, power management, and quality of service involving chip design, architecture, software, and system teams
> Architect new hardware features to improve Apple’s ability to characterize real applications and build robust online control systems for power and performance management
> Help define and create tools and workflows to collect and derive insights from terabyte-scale hardware and software trace data from prototype Apple devices
> Use hardware and software analysis tools to perform feasibility analysis for future use cases, SoCs, and products
> Assist in complex debug efforts involving system software/SoC interactions

Optimizing PerformanceNetwork on ChipPython (Programming Language)VerilogNetwork Infrastructure ArchitectureSoC Architecture+1

Carnegie mellon university

2 roles

Graduate Teaching Assistant

Aug 2022 – Dec 2022 · 4 mos · Pittsburgh, Pennsylvania, United States · On-site

Teaching Assistant for the course focusing on Lab improvements, Recitations, and occasional office hours.

Field-Programmable Gate Arrays (FPGA)Optimizing PerformanceFPGA DesignPerformance Optimization

Graduate Research Assistant

Jan 2022 – May 2022 · 4 mos · Pittsburgh, Pennsylvania, United States

Field-Programmable Gate Arrays (FPGA)Python (Programming Language)Network on ChipFPGA DesignNetwork Architecture

Nvidia

Power Architect Intern

May 2022 – Aug 2022 · 3 mos · Santa Clara, California, United States · Remote

Analyze performance and power characteristics and modeling for Deep Learning workloads on GPUs

Texas instruments

2 roles

Digital Design Engineer

Jul 2018 – Aug 2021 · 3 yrs 1 mo · Bengaluru, Karnataka, India · On-site

> Performed verification of multiple System-on-Chip peripherals, DMA, memory, and security subsystems
> Automated design and verification methodologies for consecutive spin devices for TI Wireless Connectivity products leading to an improved speed up of nearly 80 man-hours between each device
> Direct manager and mentor for an intern (Summer 2021); trained and mentored a new college graduate for 1 year (2020-21)
> Collaborated with the Applications team to provide quick software solutions for multiple client requirements and silicon bug resolutions based on the understanding of underlying hardware architecture
> Reviewed and fine-tuned specifications working with the architects and verification team for security peripherals, low-power cross-clock/power domain infrastructure, and Boot FW development for the microcontroller-based products

Digital DesignVerification

Digital Design Summer Intern

May 2017 – Jul 2017 · 2 mos · Bengaluru, Karnataka, India · On-site

Worked on the project titled "Analog Fault Coverage Analysis of Mixed Signal SoC Test Suite: Enabling Defect Based Test of Analog"
Some of this work is a part of the US Patent 20200057106, section [0029]

Indian institute of technology, bombay

Summer Intern

May 2016 – Jul 2016 · 2 mos · Mumbai Metropolitan Region · On-site

Contributed to Free and Open Source Software for Education(FOSSEE) developing functions for the Signal Processing Toolbox as part of Scilab

Iris, nitk surathkal

Co-Founder and Lead

Mar 2015 – Aug 2018 · 3 yrs 5 mos · Surathkal · On-site

IRIS (Integrated Resource and Information Sharing) system was an initiative started by me to make NITK a technologically strong university in terms of it's data management. This integrated system provides a lot of features at one place in order to make the workflow easier for students, faculties and the administration.
While leading the project, i got to work with various stakeholders - faculties, university administration, non-technical staff to understand requirements and challenges faced in offline mode of work and take appropriate decision in prioritizing development and releasing the modules that would benefits the stakeholders at large.