Ankit Garg

Software Engineer

Bengaluru, Karnataka, India11 yrs 5 mos experience

Highly Stable

Key Highlights

Over 11 years of experience in digital design and verification.
Led significant projects in audio and multimedia domains.
Expert in high-speed interfaces and verification methodologies.

Stackforce AI infers this person is a Multimedia and VLSI design specialist with extensive experience in verification and digital design.

Contact

Skills

Core Skills

LeadershipVerification And Validation (v&v)Chip LeadRtl Design

Other Skills

ArchitectureClockingCoverage AnalysisCross-functional Team LeadershipDVImage ProcessingJTAGLintLogic SynthesisMulti-site TeamsMultimediaPerlPlan ReviewPower OptimizationRobotics

About

Experienced digital design professional having more than 11 years of combined expertise of design and verification. Graduated with Bachelor of Technology (B.Tech.) focused in Electronics and Communication Engineering from IIT Roorkee. Currently working in the multimedia domain. Previously contributed to the MIPI SDCA and SoundWire standard specification while working in the audio domain at Texas Instruments. Earlier, worked at Samsung on high speed SerDes interfaces. Specialities: Leadership RTL design Synthesis Timing Analysis Lint CDC Verilog System Verilog & SVA UVM High-speed interfaces (USB, PCIe, DP, VbyOne, MIPI MPHY) UART, I2C, SPI, AMBA Protocols, I2S , MIPI Soundwire, MIPI SoundWire Device Class for Audio (SDCA), Scripting languages for automation: Perl, Python, shell scripting, TCL, Macros in excel using VBA

Experience

Amazon

Senior ASIC Design Engineer

Aug 2023 – Present · 2 yrs 7 mos · Bengaluru, Karnataka, India · On-site

Texas instruments

2 roles

Lead Digital Design Engineer

Feb 2022 – Aug 2023 · 1 yr 6 mos

Project Lead for all SoundWire and SDCA related Developments.

LeadershipVerification and Validation (V&V)

Senior Digital Design Engineer

Jan 2020 – Feb 2022 · 2 yrs 1 mo

Chip lead for Smart Audio Amplifier Products i.e. TAS2781 and TAS2783.
Worked on SoundWire v1.2 IP design, verification and validation.

Chip leadVerification and Validation (V&V)

Samsung semiconductor india r&d

3 roles

Associate Staff Engineer

Mar 2018 – Jan 2020 · 1 yr 10 mos

Worked on digital design(RTL) of RX PHY layers of Display port, VbyOne, MIPI-MPHY IPs.
Worked on CDR, CTLE, DFE, Offset & register calibration , BIST, Lane & CMN FSM blocks, SFR RTL generation.
Responsible for running LINT & CDC checks, synthesis, timing analysis and verification using Verilog testbench also.

RTL designVerification and Validation (V&V)

Senior Hardware Engineer

Promoted

Mar 2017 – Feb 2018 · 11 mos

Responsibilities :
Developed verification environment for PCIE Gen3, USB 3.1 PHY IPs using UVM methodology.
Developed a perl script to dump system Verilog assertions(SVA) mostly for timing checks.
Developed a model to generate the clock with different kinds of jitter, ssc & ppm offset to change the bit period and verified the IP functionality according to spec limits.
Developed the CDR model in TB and using that model wrote scoreboard for USB & PCIe PHYs to ensure the correct data transmission between serial and PIPE interface.
worked on RTL design of generic modules.

Verification and Validation (V&V)RTL design

Hardware Engineer

Dec 2015 – Feb 2017 · 1 yr 2 mos

Responsibilities :
Developed verification enviroment of UART , I2C, SPI ,USB 3.0 IPs using UVM methodology.
Wrote System Verilog Assertions for protocol checks and cover groups to find coverage holes.

Verification and Validation (V&V)RTL design

Hcl technologies ltd.

VLSI verification Engineer

Sep 2014 – Dec 2015 · 1 yr 3 mos · Noida Area, India

Developed testbench environment and testcases using verilog /system verilog /UVM with coverage and Assertions also.
Experience on AMBA bus protocols (APB,AHB,AXI).
Perl and shell scripting languages for automation.
Worked on emulation of designs using ZEBU emulator .

Verification and Validation (V&V)RTL design