raviteja repaka

Product Engineer

Bengaluru, Karnataka, India12 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expert in full chip timing signoff for SOCs.
  • In-depth understanding of RTL2GDSII flow.
  • Led synthesis and STA activities in teams.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Physical VerificationVLSICadence VirtuosoMBISTVerification and Validation (V&V)VerilogSimulationsSTAApplication-Specific Integrated Circuits (ASIC)Logic Synthesis

About

Owned full chip timing signoff activity for multiple SOCs. Expertise in Synthesis / timing analysis / functional eco and timing eco implementation/ constraints development and validation. Hands on experience of FV/CLP/GLS/MBIST/Physical design. Lead the team in both synthesis and STA activities. Have in depth understanding of complete RTL2GDSII flow.

Experience

12 yrs 9 mos
Total Experience
4 yrs 7 mos
Average Tenure
3 yrs 10 mos
Current Experience

Amd

SMTS Silicon Design Engineer

Jun 2022 – Present · 3 yrs 10 mos · Hyderabad, Telangana, India

Physical DesignStatic Timing AnalysisPhysical VerificationVLSICadence VirtuosoMBIST+6

Qualcomm

2 roles

Sr Lead Engineer

Nov 2020 – Sep 2022 · 1 yr 10 mos

  • STA Engineer

Senior Engineer

Jul 2017 – Nov 2020 · 3 yrs 4 mos

  • STA Engineer

Arm embedded technologies pvt. ltd.

Design Engineer

Jul 2013 – Jul 2017 · 4 yrs · Greater Bengaluru Area

Education

Indian Institute of Technology, Madras

Master of Technology (M.Tech.) — Microelecronics & VLSI Design

Jan 2011 – Jan 2013

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