Sep 2017 – Mar 2019 · 1 yr 6 mos · Santa Clara, California

• Signal and power integrity for GDDR6, GDDR6+, LPDDR5
• on-chip power delivery and SSO modeling
• power supply induced jitter
• Optimization of IO and analog front-end circuit including equalization
• IO timing budget
• Package and PCB channel design
• Lab characterization of IO jitter and model correlation
• VRM optimization and power integrity
• VR and power delivery design for graphic cards
• supply induced jitter analysis and impact of adaptive clocking
• Next generation memory interface

Jan 2016 – Apr 2017 · 1 yr 3 mos · San Jose

• DDR4 IO system link budget and chip-package-PCB co-design
• Optimize power supply noise and on-chip regulator with PDN design of chip/package
• System timing budget and circuit optimization based on jitter analysis of power supply induced jitter and IO channel timing error
• Define electrical spec (PDN, xtalk) for on-chip and package
• Provide guidance for PCB channel design and usage model based on SiPi co-simulation
• Silicon bridge design and optimize link performance for HBM and 2.5D in multi chip SiP
• U-bump, C4 bump design and bridge design to minimize SSO/SSI and xtalk
• Define power scheme and domain
• : Allocate circuit blocks to minimize power supply induced jitter
• : Define power connection (die, package or PCB) with system PDN and jitter analysis
• Optimized timing components and circuit performance based on PSIJ analysis and IO timing budget
• Define target impedance for Core and digital logics with system level PDN and jitter analysis
• Defined Vmin specification with considering 2nd and 3rd droop to ensure logic timing closure
• Defined tolerance of 1st droop and package PDN spec based on jitter analysis
• Architecture change to stagger the activity of reset assertion/de-assertion to meet the voltage ripple tolerance for core and digital IPs

Mar 2013 – Dec 2015 · 2 yrs 9 mos

• 1. Architecture level design optimization based on timing jitter analysis for high speed serial link
• Analyzed PSIJ (power supply noise induced jitter)
• Optimized circuit timing and PDN design with cost/risk analysis
• 2. DDR4 timing analysis
• System level PSIJ analysis based on DQ-DQS tracking
• 3. Timing model for digital core logics
• Vectorless core noise modeling based on randomness
• Improved model for net setup/hole timing margin loss
• 4. Characterized performance degradation of TX and RX due to power supply noise and cross talk in HSSI

Oct 2011 – Mar 2013 · 1 yr 5 mos

• 1. Developed Modeling and characterization methodology of PSIJ (power supply noise induced jitter) in HSSI and memory system
• Debugged high jitter issue due to power noise by using PSIJ modeling methodology
• Built the customized tool to calculate PSIJ with GUI (Matlab base)
• 2. Defined electrical spec. of HSSI and memory PDN for next product
• Leading a team for HSSI PDN design
• Involved in timing budget for DDR4 (PSIJ part) and HSSI
• IR drop analysis and its impact on jitter sensitivity
• 3. New characterization method development for HSSI RX
• 4. Proposed and optimized the new compensation circuits to minimize SSN for next gen.
• 5. Analysis of BUJ due to PSIJ

Feb 2010 – Apr 2010 · 2 mos · sunnyvale

• 1. Designed ball maps for HSSI package based on SI/PI analysis
• 2. Developed design guide for minimization of on-chip crosstalk, jitter and skew

Mar 2005 – Aug 2011 · 6 yrs 5 mos · Yuseong-gu, Daejeon, Korea

• 1. Analyzed power integrity effects on clock jitter and performance of analog devices with fast and precise modeling including circuit, chip, package and PCB
• 2. Designed the compact and wide band passive equalizer for 10Gbps
• 3. Modeling and analysis of coil for wireless power transportation
• 4. Characterization and Design Optimization of Through Silicon Vias (TSVs) for Signal/Power Integrity in 3D IC (IMEC, Belgium)
• 5. Chip-Package-PCB Co-Design for High Performance System ( UHF RFID and X/Ku band Transceiver) Linked with FPGA (Stratix II)
• Design DAC and base band modem
• Design package and integration of the full chip