Gregory Gruber — Software Engineer

• Physical and circuit design engineer with extensive experience designing high-speed, low-power, digital chips spanning many sub-micron technology nodes (including 3nm, 5nm, 7nm, 10nm, and 16nm FinFET plus older planar nodes) • Senior manager and technical lead for low-power and high-performance standard cell libraries across a wide range of technology nodes (3nm to 130nm) supporting aggressive customer specs. Cross-functional and cross-location collaboration with customers and with headquarters in Taiwan. • Manager and technical lead for high-performance standard cell libraries supporting all aspects of SPARC chips in 7nm - 28nm nodes, including cross-functional collaboration with 200+ member design team • Owned physical design of cells, including layout and strategies for pinning, abutment, and emir; optimized cell tradeoffs in performance, power, area, and robustness; cell characterization for timing, power, emir, sigem, and noise with full support for cluster physical design tools • Flop design lead, including innovating new low-power and high-speed flops to meet aggressive power, performance, area, and robustness targets. Schematic and layout co-optimization. • Trailblazer for evaluation and deployment of 3nm–16nm FinFET nodes: design rules and layout optimization, dual-patterned metals, via ladders, technology scaling, extraction methodology, emir strategies, spice simulations, and trends/dependencies in transistor performance • Drove static timing analysis (STA) closure and enhancements with advanced modeling (AOCV, POCV, CCS Noise) • Physical design with Synopsys tool suite • Backend tools and physical verification, including emir, sigem, noise, LVS/DRC/ERC/ANT • Physical design of parity logic, adders, incrementers, encoders, decoders, and other megacells from RTL to GDS • Led extraction methodology and verification/QA, including transistor layout-dependent effects • Highly motivated and results-oriented leader with strong analytical skills and superior communication. Proven ability to collaborate across many functions and plan resources to meet aggressive schedules.

Stackforce AI infers this person is a semiconductor design expert with a focus on digital circuits and low-power technologies.

Location: San Jose, California, United States

Experience: 31 yrs 6 mos