Snehil Verma

DevOps Engineer

Cupertino, California, United States8 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in hardware acceleration and computer architecture.
Proven experience in deep learning performance evaluation.
Strong collaboration skills with cross-functional teams.

Stackforce AI infers this person is a specialized expert in hardware acceleration and computer architecture within the technology sector.

Contact

snehilv@utexas.edu LinkedIn

Skills

Core Skills

Hardware AccelerationComputer Architecture

Other Skills

ArduinoArdupilotBashCC#C++CUDACactiCadence VirtuosoCompilersComputer HardwareDeep LearningDocker ProductsEvent PlanningGNU Octave

About

I am an M.Sc. student in Electrical & Computer Engineering at the University of Texas at Austin. My advisor is Prof. Lizy K. John, and I am affiliated with the Laboratory for Computer Architecture (LCA). My research focuses on Computer Architecture, specifically on performance evaluation of Machine Learning workloads. I completed my bachelor's degree in Electrical Engineering from the Indian Institute of Technology Kanpur in 2018. For more details, please visit my homepage at:

Experience

Apple

Senior Deep Learning Hardware Acceleration Engineer

Jul 2020 – Present · 5 yrs 8 mos

Affiliated with Apple Neural Engine's Compiler Team.
Architected/developed the compiler for ANE to enable DL applications (including Vision Transformers and LLMs) on Apple products with an emphasis on performance and power.
Brought up new hardware silicon and added support for new hardware features in the compiler.
Collaborated with Firmware, Driver, and Platform Architecture teams to achieve the functional and performance goals of various hardware blocks. Also, worked on the definition of new hardware features with the Platform Architecture team.
Contributed to the auxiliary software stack and tooling to support testing and debugging of neural networks.

CompilersHardware AccelerationComputer Architecture

Cockrell school of engineering, the university of texas at austin

2 roles

Graduate Teaching Assistant

Jan 2020 – May 2020 · 4 mos

EE382V - Hardware Architectures for Machine Learning (taught by Prof. Lizy K. John)

Graduate Research Assistant

Aug 2018 – Jun 2020 · 1 yr 10 mos

Advised by Prof. Lizy K. John and affiliated with the Laboratory for Computer Architecture (LCA).
FastPath, ISPASS'19: Proposed a new metric for benchmarking ML workloads from the perspective of comparing training hardware.
NVIDIA GTC'19: An extensive study on the impact of hardware infrastructure choices on deep learning performance for training.
arXiv e-print: Analyzed and characterized the MLPerf [v0.5] training benchmark suite exposing various system-level trends.

Samsung electronics

2 roles

GPU Software Intern

Sep 2019 – Dec 2019 · 3 mos

Affiliated with Software, ML Strategic Planning, and Workload Characterization team at Samsung SARC, Austin.
Equipped the OpenCL drivers’ team with a tool capable of capturing, tailoring, and replaying the OpenCL API trace.
Utilized Samsung's proprietary OpenCL Layers and coded a generic library to manage the file input/output efficiently.
Performed an in-depth study on AI Benchmarks and compute workloads, identifying their hot-spots.

GPU Power Performance and Area (PPA) Intern

May 2019 – Aug 2019 · 3 mos

Affiliated with PPA (Power, Performance, and Area) and Architecture team at Samsung ACL, San Jose.
Executed power/performance flows on SoC emulation platform to identify performance bottlenecks and blocks using high power.
Developed microbenchmarks targeted at specific architectural features, and initiated the research on ML-based power prediction.
Delved into the design exploration of Texture Cache, analyzed its performance, and studied SOTA Texture Compression techniques

Texas a&m university college of engineering

Visiting Research Scholar

Jun 2017 – Jul 2017 · 1 mo · Bryan/College Station, Texas Area

Advised by Prof. Eun J. Kim and affiliated with the High Performance Computing Lab (HPCL).
Proposed and modeled Coherence-Aware Reuse Prediction on ZSim that achieved a speedup of 20% over LRU when evaluated on the PARSEC benchmark suite.

Counselling service, iit kanpur

Academic Mentor

Jul 2015 – Apr 2016 · 9 mos · Kanpur Area, India

• Tutored students having difficulties in Engineering Design and Graphics by conducting institute level remedial classes and doubt-clearing sessions. Personally mentored academically weaker students to cope with their academic load.

Antaragni iit kanpur

Media Marketing and Publicity Executive

May 2015 – Oct 2015 · 5 mos · IIT Kanpur

Worked in a 10-memberd strong team of Executives, responsible for publicity and media coverage of the festival
Co-ordinated and negotiated with over 20 companies for festival sponsorship and finalized deals with them