Paresh Kurdekar — Operations Associate
Master's student in Electrical and Computer Engineering at UC San Diego, specializing in FPGA and ASIC digital design, RTL development, and hardware acceleration. I bring 2+ years of hands-on experience in high-performance computing, having contributed to the National Supercomputing Mission through FPGA based NIC design. I’ve worked across the full hardware design stack, from RTL coding and floorplanning to timing closure and validation, and recently interned at Juniper Networks on HBM controller development. I enjoy working at the intersection of performance and precision, whether it's closing timing on a complex design or optimizing logic to meet tight constraints. I'm excited to take the next step into a full time role in ASIC or FPGA design, where I can keep solving real hardware challenges and contribute to impactful, production-grade systems.
Stackforce AI infers this person is a Semiconductor and Robotics specialist with a focus on FPGA and ASIC design.
Location: La Jolla Shores, California, United States
Experience: 3 yrs 2 mos
Skills
- Rtl Design
- Computer Architecture
- Asic Design
- Verification
- Circuit Design
- Fpga Design
- Software Development
Career Highlights
- 2+ years in high-performance computing and FPGA design.
- Contributed to national supercomputing mission through NIC design.
- Expertise in RTL development and hardware acceleration.
Work Experience
UC San Diego
Teaching Assistant (2 mos)
Juniper Networks
ASIC Design Intern (3 mos)
Marine Physical Laboratory
Laboratory Assistant (5 mos)
Centre for Development of Advanced Computing (C-DAC)
Project Engineer (2 yrs 1 mo)
ICICI Lombard
Developer (10 mos)
Technology Intern (6 mos)
Education
Master's degree at UC San Diego Jacobs School of Engineering
Bachelor of Technology at Manipal Institute of Technology
