Gobind Prasad — Software Engineer
Experienced in RTL Design & Verification, Microarchitecture development, synthesizable RTL design for high speed protocols like MIPI, USB and AMBA. - MIPI : implemented several features in RTL for palladium emulator BFM, debugging and verification of several features. - DisplayPort : Verification of several features like DSC, FEC, enhanced, non enhanced framing modes etc. - USB : Designed a complete eUSB2 Phy Layer from scratch with Encoding/Decoding, bit stuffing/unstuffing and Serdes along with low power features implementation, and did verification of the same over USB3.1 fabric in Xcelium simulator and Palladium emulator for all types of transaction (bulk, isochronous, interrupt and control transfers) and low power verification (sleep/suspend). - USB4 : verification of TMU and several blocks of Transport & Logical layer. - Good skills in Hardware architecture, RTL design, Verilog, System Verilog and digital design fundamentals and ASIC/SOC design flow. - Familiar with Emulator Palladium, Protium, Xcelium, Questa Sim, Orcad, Matlab tools. - Knowledge of UVM based constrained driven verification. - Completed Course on Emulation using VELOCE by Siemens (Mentor Graphics). Earlier experience as R&D engineer (PCB HW domain) - Designing HW architecture, Analog Circuit design/simulation & schematics creation in Cadence Orcad tool - Component selection for product (processor, ADC/DAC, sensors, power supply, battery pack, wire harness etc.) - PCB Board Verification & Design Verification using high frequency DSO/logic analysers. - Risk analysis (DFMEA/CFMEA), Stress Analysis, Value Engineering Value Analysis for the products/Module/PCBs.
Stackforce AI infers this person is a specialist in RTL Design and Verification within the semiconductor industry.
Location: Noida, Uttar Pradesh, India
Experience: 11 yrs 4 mos
Skills
- Rtl Design
- Verification
- Rtl Verification
- Analog Circuit Design
- Debugging
Career Highlights
- Expert in RTL Design and Verification for high-speed protocols.
- Designed eUSB2 PHY Layer with comprehensive verification.
- Proficient in UVM-based constrained driven verification.
Work Experience
Cadence Design Systems
Principal Software Engineer (5 yrs 8 mos)
Altran
ASIC Verification Engineer (1 yr)
HCL Technologies
Member Of Technical Staff (1 yr 9 mos)
Hardware Design Engineer (1 yr 8 mos)
Hardware Design Trainee (1 yr 3 mos)
NTPC
Industrial Trainee (2 mos)
Education
Bachelor of Technology (BTech) at Indian Institute of Technology, Delhi