Gobind Prasad

Software Engineer

Noida, Uttar Pradesh, India11 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL Design and Verification for high-speed protocols.
  • Designed eUSB2 PHY Layer with comprehensive verification.
  • Proficient in UVM-based constrained driven verification.
Stackforce AI infers this person is a specialist in RTL Design and Verification within the semiconductor industry.

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Skills

Core Skills

Rtl DesignVerificationRtl VerificationAnalog Circuit DesignDebugging

Other Skills

LinuxLogic DesignSystem VerilogVerilog HDLIP VerificationDisplayPortHardware VerificationTest PlanningSiliconComputer SimulationsPHYMIPIUSBAnalytical SkillsObject-Oriented Programming (OOP)

About

Experienced in RTL Design & Verification, Microarchitecture development, synthesizable RTL design for high speed protocols like MIPI, USB and AMBA. - MIPI : implemented several features in RTL for palladium emulator BFM, debugging and verification of several features. - DisplayPort : Verification of several features like DSC, FEC, enhanced, non enhanced framing modes etc. - USB : Designed a complete eUSB2 Phy Layer from scratch with Encoding/Decoding, bit stuffing/unstuffing and Serdes along with low power features implementation, and did verification of the same over USB3.1 fabric in Xcelium simulator and Palladium emulator for all types of transaction (bulk, isochronous, interrupt and control transfers) and low power verification (sleep/suspend). - USB4 : verification of TMU and several blocks of Transport & Logical layer. - Good skills in Hardware architecture, RTL design, Verilog, System Verilog and digital design fundamentals and ASIC/SOC design flow. - Familiar with Emulator Palladium, Protium, Xcelium, Questa Sim, Orcad, Matlab tools. - Knowledge of UVM based constrained driven verification. - Completed Course on Emulation using VELOCE by Siemens (Mentor Graphics). Earlier experience as R&D engineer (PCB HW domain) - Designing HW architecture, Analog Circuit design/simulation & schematics creation in Cadence Orcad tool - Component selection for product (processor, ADC/DAC, sensors, power supply, battery pack, wire harness etc.) - PCB Board Verification & Design Verification using high frequency DSO/logic analysers. - Risk analysis (DFMEA/CFMEA), Stress Analysis, Value Engineering Value Analysis for the products/Module/PCBs.

Experience

Cadence design systems

Principal Software Engineer

Jul 2020Present · 5 yrs 8 mos · Noida, Uttar Pradesh, India

LinuxLogic DesignRTL DesignVerification

Altran

ASIC Verification Engineer

Jul 2019Jul 2020 · 1 yr · Noida Area, India

System VerilogRTL VerificationVerification

Hcl technologies

3 roles

Member Of Technical Staff

Promoted

Oct 2017Jul 2019 · 1 yr 9 mos

Verilog HDLAnalog Circuit DesignRTL Design

Hardware Design Engineer

Jan 2016Sep 2017 · 1 yr 8 mos

Analog Circuit DesignDebugging

Hardware Design Trainee

Sep 2014Dec 2015 · 1 yr 3 mos

Ntpc

Industrial Trainee

May 2013Jul 2013 · 2 mos · Badarpur

  • Analyzed the HT Motors on the basis of current and vibration signature, to minimize the problems of continuous and periodic noise and vibration.

Education

Indian Institute of Technology, Delhi

Bachelor of Technology (BTech) — Electrical Engineering

Jan 2010Jan 2014

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