Muneesh Yadav

Software Engineer

Gurugram, Haryana, India3 yrs 5 mos experience

Key Highlights

Expert in Python-based EDA automation for IC design.
Automated backend QA verification processes, enhancing efficiency.
Expanding skills into SKILL scripting and physical verification.

Stackforce AI infers this person is a Backend-focused EDA Automation Engineer in the semiconductor industry.

Contact

Skills

Core Skills

Cadence SkillPython (programming Language)Circuit DesignShell ScriptingRtl Coding

Other Skills

AllegroArduinoBashC (Programming Language)C++Cadence VirtuosoHTMLLayout DesignLinuxRTL DesignRTL VerificationSystemVerilogTCLVerilogdraw.io

About

I specialise in building Python-based backend EDA automation flows for IC design collateral conversion, design QA, property extraction, and report generation. With experience working across Cadence Allegro and Virtuoso platforms, I’ve contributed to automating design data pipelines and backend QA verification processes for mixed-signal design teams. I’m currently expanding my capabilities into SKILL scripting and physical verification automation, and actively seeking CAD Methodology, EDA Automation, or Backend Flow Development roles in semiconductor or EDA companies.

Experience

Uandwe, inc.

CAD Engineer

Jul 2025 – Present · 8 mos · Bengaluru, Karnataka, India · Remote

Cadence SkillPython (Programming Language)Cadence Virtuoso

Yoctozant technologies

CAD - CPSE Engineer

Aug 2023 – Jun 2025 · 1 yr 10 mos · India · Remote

Deployed on the client.

Python (Programming Language)BashCadence SkillC++TCLCadence Virtuoso

Analog devices

CAD - CPSE Engineer

Aug 2023 – Apr 2025 · 1 yr 8 mos · Bengaluru, Karnataka, India · On-site

Developed backend Python-based EDA flows for design collateral conversion between Allegro and Virtuoso environments.
Automated property extraction, mapping, and verification of Allegro layout data for seamless integration into Virtuoso flows.
Built QA automation scripts to validate layout symbol consistency and property mappings.
Generated HTML-based reporting systems to track unmapped symbols and assist designers with debugging.
Optimised flow performance via incremental processing, reducing execution time by ~80%.
Supported backend design automation tasks that reduced manual design cleanup effort for mixed-signal IC teams.

Cadence SkillCadence VirtuosoPython (Programming Language)BashAllegro

Pine training academy of vlsi & embedded

Trainee

Sep 2022 – Aug 2023 · 11 mos · Noida, Uttar Pradesh, India · On-site

Completed a full-time, 1-year VLSI training program at Pine Training Academy, focusing strongly on ASIC design fundamentals. The curriculum included hands-on modules in analog circuit design, analog layout, memory layout, TCL scripting, and Bash scripting, providing a solid foundation in front-end and back-end VLSI concepts.

Circuit DesignShell ScriptingLayout DesignVerilog

Aceic design technologies

Internship Trainee

Jun 2020 – Jun 2020 · 0 mo · India

Learned about VLSI Design Flow, and mainly focused on Project specification analysis, Design Architecture, RTL coding in Verilog, and Synthesis.
Worked on projects: the half adder, full adder, gates, 4x1 multiplexer, decoder, and Bridge Top of APB protocol.

RTL Coding