Apurba Paul

Software Engineer

India4 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL design and digital circuit development.
  • Proficient in Xilinx Vivado and Verilog.
  • Strong background in PCIe and Ethernet technologies.
Stackforce AI infers this person is a skilled engineer in digital design and RTL development within the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Rtl DevelopmentDigital Circuit Design

Other Skills

Digital DesignsVerilogXilinx VivadoSystemVerilogQuestaSimField-Programmable Gate Arrays (FPGA)EnglishControl Systems DesignElectrical WiringEmbedded SystemsEmbedded CC (Programming Language)CommunicationFuzzy SystemsWireless Sensor Networks

Experience

Qbit labs private limited

4 roles

Senior Engineer

Promoted

Apr 2024 – Present · 1 yr 11 mos

  • RTL design, PCIe, Ethernet, TSN
Digital DesignsVerilogRTL DevelopmentDigital Circuit Design

RTL Design- R & D Engineer Il

May 2022 – Apr 2024 · 1 yr 11 mos

Xilinx VivadoRTL Development

RTL Design- R & D Engineer l

Jun 2021 – May 2022 · 11 mos

Xilinx VivadoRTL Development

Summer Intern

Dec 2020 – Jun 2021 · 6 mos

Xilinx VivadoSystemVerilogRTL Development

Indian institute of technology, delhi

Research Intern

Jun 2020 – Jun 2020 · 0 mo · Delhi, India

Education

National Institute of Technology , Patna

Electrical Engineering — Electric vehicles

Jan 2017 – Jan 2021

St. Joseph's convent high school

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