Avinash Chavan — Software Engineer
Hello, Senior RTL designer with 8+ years of experience in RTL (ASIC & FPGA) design in VHDL, Verilog and System Verilog including below tasks: • Developing architecture design and micro architecture design. • Developing RTL code for various IP’s. • Developing Synthesis constraints and error free synthesis RTL. • STA & RTL quality checks. • Lint/CDC/RDC checks. EDA Tools : Xilinx ISE14.7, Vivado, Spyglass, Design Compiler. Languages : Verilog, VHDL, System Verilog. Protocol : SPI, UART, AMBA(AHB-APB), AXI-4, PCIE & Ethernet. Digital Design Circuits & writing RTL and TEST-BENCH code. Synthesize and Simulation of RTL design in both ASIC and FPGA flow. Knowledge of scripting language Perl. Knowledge of Spyglass Lint / CDC. Knowledge of debugger like Xilinx ILA & Chipscope, Vivado Analyzer
Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and FPGA development.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 8 mos
Skills
- Asic Design
- Functional Verification
- Vlsi Design
Career Highlights
- 8+ years of experience in RTL design.
- Expertise in ASIC and FPGA design.
- Proficient in multiple hardware description languages.
Work Experience
Sintegra Inc.
ASIC Design Engineer @ client: Meta (1 yr 4 mos)
Tata Consultancy Services
ASIC Design Engineer (2 yrs 2 mos)
Wipro Limited
Senior RTL Design Engineer (1 yr 5 mos)
Modsonic Instruments Manufacturing Company Pvt Ltd
FPGA Design Engineer (3 yrs 4 mos)
Maven Silicon
Internship (2 mos)
VLSI Design and Verification Trainee (5 mos)
Education
Engineer’s Degree at University of Mumbai
PG-Diploma at Maven Silicon Softech Pvt. Ltd.
HSC at PVG Vidya bhawan jr college
SSC at vanita mandal's Vikas Vidyalaya.
