Navya Singla

Software Engineer

Timnath, Colorado, United States4 yrs 6 mos experience

Most Likely To Switch

Key Highlights

Expert in low power design verification and implementation.
Proven track record in optimizing physical design processes.
Skilled in automation for low power checks and reporting.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in low power design and verification.

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Skills

Core Skills

Physical DesignFunctional Verification

Other Skills

PrimetimeLECRTL DesignSynopsys PrimetimeField-Programmable Gate Arrays (FPGA)Timing ClosureUnified Power Format (UPF)Static Timing AnalysisDigital Circuit DesignLow Power SignoffRTL DevelopmentGate Level SimulationSystemVerilogLogic DesignCPU design

About

Understanding of netlist to GDS2 implementation. Hand-o experience on timing closure activities to meet performance targets and power analysis, optimization efforts to achieve low-power designs. Experienced Engineer with a demonstrated history of working in low power design verification. Skilled in CLP (Conformal low power checks ) which detects low power implementation errors early in design cycle. Enabled low power implementation methods using UPF.( Multiple voltages, multiple power domain, and power gating techniques). - Research Interests: VLSI Design, Physical Design, Low Power SRAMs, Low Power Computing, Electronic Design Automation, Computer Architecture - Programming and Scripting Languages: Python, TCL, C - Hardware Description Language: Verilog, System Verilog, VHDL - EDA Tools: Synopsys Primetime, Design Compile, Cadence conformal low power, LEC

Experience

4 yrs 6 mos

Total Experience

2 yrs 3 mos

Average Tenure

2 yrs 4 mos

Current Experience

Amd

Senior Physical Design Engineer

Jan 2024 – Present · 2 yrs 4 mos · Fort Collins, Colorado, United States · On-site

Qualcomm

3 roles

GPU Physical Design intern

May 2023 – Aug 2023 · 3 mos · San Diego, California, United States · On-site

Engineered an ECO generation flow using PD Solver, eliminating hold buffers based on available margin
Achieved a 30% runtime boost over tweaker without impacting timing
Trimmed standard cell utilization on production DB by 1.5% at ECO stage while upholding PPA metrics

Physical DesignPrimetime

Low power Engineer

Promoted

Nov 2021 – Aug 2022 · 9 mos · Bengaluru, Karnataka, India

Responsible for sign-off SOC level low power checks
Signed-off 4 SOCs for formal and low power checks
Developed an automation to set golden reports for batch mode setup as part of low power checks
Provided Conformal LEC training to a new college graduate.

Functional VerificationLEC