Md Faizan khan — CTO
RTL Design Engineer with over 4 years of experience in RTL design, FPGA prototyping, and digital system development. Proven expertise in designing and implementing physical layer logic for high-speed protocols including PCIe Gen5/Gen6 and CXL 2.0/3.0. Skilled in System Verilog, Verilog, VHDL, timing closure, CDC analysis, and board-level debugging on Xilinx FPGA platforms. Proven track record of delivering complex FPGA-based designs with optimized performance and resource usage.
Stackforce AI infers this person is a VLSI design engineer specializing in FPGA prototyping and digital system development.
Location: Gorakhpur, Uttar Pradesh, India
Experience: 3 yrs 7 mos
Skills
- Pcie
- Cxl
- Rtl Design
- Vhdl
- Rtl Coding
- Vlsi
- Digital Electronics
- Verilog
Career Highlights
- Expert in high-speed protocol design including PCIe and CXL.
- Proven track record in delivering optimized FPGA designs.
- Strong foundation in RTL design and debugging techniques.
Work Experience
Logic Fruit Technologies
Lead Engineer (11 mos)
Senior R&D Engineer (1 yr 2 mos)
R&D Engineer (11 mos)
R&D Engineer- Trainee (9 mos)
R&D Intern in FPGA Department (5 mos)
Birla Institute of Technology, Mesra
Final year project (3 mos)
Maven Silicon
Digital VLSI Design Intern (1 mo)
Education
Bachelor of Technology - BTech at Birla Institute of Technology, Mesra
Intern at Maven Silicon
Senior School Certificate Examination at Oxford Public School Gorakhpur
Secondary School Examination at Delhi Public Convent School Baheri Ballia
