Satish vishnumolakaka

Software Engineer

India7 yrs 4 mos experience

Highly Stable

Key Highlights

Expert in PCIE and CXL protocol verification.
Strong background in system verilog and UVM methodologies.
Proven leadership in semiconductor design verification.

Stackforce AI infers this person is a semiconductor verification engineer with expertise in PCIE and CXL protocols.

Contact

Skills

Core Skills

System VerilogUniversal Verification Methodology (uvm)PcieCxl

Other Skills

LinuxPCIE Gen6CXL 3.1SPI Flashlink trainingLTSSM state debuggingCXL 1.1CXL 2.0CXL 3.0PCIE Gen1PCIE Gen5Microsoft ExcelMicrosoft OfficeMicrosoft WordCustomer Service

About

Experienced Design Verification Engineer with a demonstrated history of working in the semiconductors industry. Strong engineering professional skilled in system verilog, Universal Verification Methodology (UVM), perl,pcie gen3, pcie gen4, pcie gen5, gen6,CXL 1.1,CXL2.0, Cxl 3.0, Usb 2.0, Linux, amba protocols like ahb,axi,apb, hardware securityprotocol, knowledge of gls. knowledge of spi, uart, i2c protocol, DDR4 protocol, Emulation (veloce platform) .

Experience

7 yrs 4 mos

Total Experience

2 yrs

Average Tenure

2 mos

Current Experience

Marvell technology

Senior Staff Engineer

Mar 2026 – Present · 2 mos · Hyderabad, Telangana, India · On-site

system verilogUniversal Verification Methodology (UVM)Linux

Quest global

Senior Lead Engineer

May 2025 – Mar 2026 · 10 mos · Bengaluru, Karnataka, India · Remote

PCIE Gen6, CXL 3.1,SPI Flash
I have hands-on experience in the PCIE protocol, including Gen1 to Gen6,focusing on link training, LTSSM state debugging, PCIE Equalization,PCIE Lane reversal, PCIE TLP traffic, PCIE reset(Hot reset, cold reset, warm reset,FLR ), TLP/DLP packet analysis, error handling (link down, LCRC), PCIE ACS, PCIE Enumeration, ECC (Single bit error(SEC), double bit error detection (DED).
I have worked on CXL verification and analysis, focusing on CXL.io, CXL.mem protocols. This includes CXL 1.1 , CXL 2.0, CXL 3.0, CXL 3.1 features such as memory pooling, CXL.io traffic, CXL.mem traffic,Type2/3 devices across host and device subsystems.

PCIE Gen6CXL 3.1SPI FlashPCIECXL