Mukul Mehta

Software Engineer

Bengaluru, Karnataka, India8 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in RTL design for ASIC and FPGA.
Proficient in low-power design and micro-architecture.
Skilled in functional verification and timing closure.

Stackforce AI infers this person is a specialized RTL design engineer in the semiconductor industry.

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Skills

Core Skills

Rtl DesignSystem On A Chip (soc)Logic SynthesisMicro-architecture

Other Skills

ARM Coresight ArchitectureActive ListeningAdobe PhotoshopAdobe Premiere ProBash shell scriptingCDCCollaborative Problem SolvingComputer ArchitectureCreative Problem SolvingDebug & TraceDecision-MakingField-Programmable Gate Arrays (FPGA)GitIP DesignInterpersonal Communication

About

RTL design engineer with experience in ASIC and FPGA domain.

Experience

Google

Silicon Engineer

Jul 2021 – Present · 4 yrs 8 mos · Bengaluru, Karnataka, India · On-site

RTL DesignVerilogPerlMicro-ArchitectureGitLint+7

Samsung electronics

Engineer

Mar 2020 – Jun 2021 · 1 yr 3 mos · Noida, Uttar Pradesh, India

Worked on hardware accelerator design.

RTL DesignVerilogPerlMicro-ArchitectureLintSystem Verilog+3

Logic-fruit technologies

R&D Engineer

Mar 2018 – Mar 2020 · 2 yrs

1. Writing synthesisable RTL code
2. Micro-architecture design
3. Functional simulation & debugging
4. Logic synthesis and implementation while achieving timing closure targeted for Xilinx FPGAs
5. Worked on design of CXL Exerciser, GenZ Jammer. Used PCIe Physical Layer in both
6. Designed Rx of SPI 4.2 IP

RTL DesignVHDLVerilogMicro-ArchitectureSystem VerilogVim+1