Gangadhar N

Software Engineer

Tenali, Andhra Pradesh, India4 yrs 7 mos experience
Highly Stable

Key Highlights

  • Experienced in FPGA RTL Design and protocol implementation.
  • Proficient in Verilog and various communication protocols.
  • Strong foundation in Digital Electronics and Electrical Engineering.
Stackforce AI infers this person is a Digital Electronics Engineer with expertise in FPGA and protocol design.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignFpga

Other Skills

VerilogPCIeDisplay PortAHBAPBAXITimingLattice RadiantElectrical EngineeringQuestaSimAMBA AHBC (Programming Language)MATLABField-Programmable Gate Arrays (FPGA)ModelSim

About

Curious to learn New things about Digital Electronics.Had experience in FPGA RTL Design. I have worked on Display port Protocol and AMBA protocols.

Experience

Qualcomm

Senior RTL Design Engineer

Oct 2024 – Present · 1 yr 5 mos

Logic fruit technologies

R&D Engineer

Jul 2021 – Sep 2024 · 3 yrs 2 mos · Bengaluru, Karnataka, India

  • I have experience in RTL Design for FPGA.I have worked on PCIe, Display Port.I have also used AHB,APB,AXI protocols.
VerilogPCIeRTL DesignFPGA

Andhra pradesh power generation corporation limited

Industrial Trainee

Jun 2019 – Jun 2019 · 0 mo · Vijayawada, Andhra Pradesh, India

Education

Visvesvaraya National Institute of Technology

Bachelor's degree — Electrical and Electronics Engineering

Jan 2017 – Jan 2021

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