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Anant Saxena

Lead IOS Developer

Bengaluru, Karnataka, India8 mos experience

Key Highlights

  • Strong foundation in Microelectronics from BITS Pilani.
  • Experience as a Graduate Teaching Assistant in multiple laboratories.
  • Internship at MediaTek focusing on RTL design.
Stackforce AI infers this person is a Microelectronics specialist with teaching experience in academic settings.

Contact

LinkedIn

Skills

Core Skills

VerilogFpga

Other Skills

Field-Programmable Gate Arrays (FPGA)

Experience

8 mos
Total Experience
8 mos
Average Tenure
--
Current Experience

Mediatek

RTL Design Intern

Jan 2025 – Jun 2025 · 5 mos · On-site

Birla institute of technology and science, pilani - goa campus

3 roles

Graduate Teaching Assistant

Aug 2024 – Dec 2024 · 4 mos · South Goa · On-site

  • HDTA for Reconfigurable Computing Laboratory
VerilogField-Programmable Gate Arrays (FPGA)FPGA

Graduate Teaching Assistant

Jan 2024 – Apr 2024 · 3 mos · South Goa, Goa, India

  • HDTA for Power Electronics Laboratory

Graduate Teaching Assistant

Aug 2023 – Dec 2023 · 4 mos · South Goa, Goa, India

  • HDTA for Electrical Machines Laboratory

Education

Birla Institute of Technology and Science, Pilani - Goa Campus

Master of Engineering - MEng — Microelectronics

Aug 2023 – Jul 2025

VIT Vellore

Bachelor of Technology - BTech — Electrical and Electronics Engineering

Jun 2017 – Jun 2021

Navrachana International School

High School Diploma — International Baccalaureate Diploma

Jan 2004 – Jan 2017

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