Naveen Srivastava

CEO

Bengaluru, Karnataka, India17 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

17+ years of expertise in HW accelerator architecture.
Strong background in SoC power analysis and design.
Proven leadership in imaging hardware design projects.

Stackforce AI infers this person is a seasoned expert in semiconductor design and architecture, specializing in imaging and power management.

Contact

Skills

Core Skills

Asic ArchitectureImaging Hw DesignSoc Power AnalysisMicroarchitectureRtl Design

Other Skills

ASIC Architecture powerclock and resetASIC Power modelingCamera Subsystem DesignHLSHardware LeadSystem CPower LeadFunctional SafetySoC Power LeadLeakage and Dynamic Power AnalysisClock tree Power Analysis and OptimizationMicroarchitecture and RTL designPost Silicon DebugSynthesis

About

17+ years strong hands on, HW accelerator Architecure and Design, NPU subsystem IP Architecture and design, Camera Subsystem Design, Digital Design, technical experience in HLS, Imaging IP design using SYSTEM C, Microarchitecture, IP Design, SoC Design. Strong Expertise in SoC Power Analysis. Strong Expertise in SoC Clock and Reset design, Post Silicon Debug, SoC Debug Flow Design. Imaging Algo HW Designer, HW Design in System C. Verilog generation through Stratus High Level Synthesis Tool. Microarchitecture Changes to meet Area Goals. Specialties: Power Architecture, HLS, Canera HW design, SoC Power Analysis, Pre Silicon Power projection and post Silicon power co-relation, Microarchitecture, RTL design, SoC Clock and Reset design, Timing Constraints/ analysis

Experience

Samsung electronics

4 roles

Principal Architect

Feb 2026 – Present · 1 mo

Architect

Apr 2023 – Present · 2 yrs 11 mos

Architect

Promoted

Apr 2023 – Present · 2 yrs 11 mos

Architect

Apr 2023 – Mar 2026 · 2 yrs 11 mos

Intel corporation

System Architecture

Jan 2018 – Apr 2023 · 5 yrs 3 mos · Bengaluru, Karnataka, India · On-site

ASIC Architecture power , clock and reset. ASIC Power modeling, Imaging HW Design, Camera Subsystem Design, HLS, Hardware Lead, System C, Power Lead, Functional Safety

ASIC Architecture powerclock and resetASIC Power modelingImaging HW DesignCamera Subsystem DesignHLS+5

Texas instruments

Design Lead

Aug 2017 – Jan 2018 · 5 mos · Bengaluru Area, India

Qualcomm innovation center inc

Lead Design Engineer

Jan 2012 – Aug 2017 · 5 yrs 7 mos · Bengaluru Area, India

1. As SoC Power Lead , Leakage and Dynamic Power Analysis, Clock tree Power Analysis and Optimization, Power projection and co-relation.
2. Microarchitecture and RTL design of Fully HW based System Power Management IP for IOT product. SoC fully HW based Clock Microarchitecture for IOT product.
3. RTL design for HW Based External serial Device to DDR data transfer Module,
4. SoC Clock and Reset design, SoC Clock Constraint creation, Floor Plan guidelines, CTS guidelines for low clock tree power.
5. Post Silicon Debug of designed IPs

SoC Power LeadLeakage and Dynamic Power AnalysisClock tree Power Analysis and OptimizationMicroarchitecture and RTL designPost Silicon DebugSoC Power Analysis+1

Stmicroelectronics

Sr. Design Engineer

Mar 2010 – Dec 2011 · 1 yr 9 mos · Greater Noida

RTL Design for DDR3 controllers, Cache Controller, MultiMedia Card Controllers, Access Control IPs, Memory Encryption IPs
RTL design, Synthesis, Timing Analysis

RTL DesignSynthesisTiming Analysis