Jayadev Devagiri

Software Engineer

Gadag, Karnataka, India11 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Gold medalist in VLSI from IIITH
  • Expertise in low power IOT WLAN chip design
  • Proven track record in RTL development for SOCs
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and wireless communication.

Contact

LinkedIn

Skills

Core Skills

Vlsi DesignRtl DevelopmentWifi DesignWireless Communication

Other Skills

VerilogLINTCDCUPFPalladiumRTL codingMatlabCVLSIVHDLPythonCadenceMicrocontrollersCadence VirtuosoDigital Electronics

About

RTL Design engineer with experience from micro architecture to post silicon bring up. Worked on the low power IOT WLAN chips to the high performance discrete graphics SOC team. Good technical background in VLSI design with Masters(Gold medal) from IIITH in VLSI and CE. Notable experience and skills include: - Low Power Design - Micro architecture - All aspects of VLSI FLow RTL design, Verification(Verdi/UVM), Emulation(Palladium), Post Si Bring up - CDC/LINT flow - UPF strategies - IEEE 802.11 protocol - ECO implementation with FEV clean up

Experience

Intel corporation

2 roles

GPU SOC Design engineer

May 2025 – Present · 10 mos · Bangalore Urban, Karnataka, India

Soc design engineer

Jul 2018 – Mar 2023 · 4 yrs 8 mos · Bengaluru Area, India

  • Took a challenging task of RTL development for Foveros Die to Die interconnect and was responsible for LINT,CDC, UPF delivery to the SOC team.
  • Involved in GPIO subsystem RTL development of Discrete graphics SOCs.
  • PCIE Subsystem RTL integration to the SOC
VerilogRTL Development

Memryx inc.

Lead Design Engineer

Nov 2022 – May 2025 · 2 yrs 6 mos · Bengaluru, Karnataka, India

VerilogVLSI Design

Cypress semiconductor corporation

Sr Elect Design Engr, DCD: WIFI Design India

Jul 2016 – Jul 2018 · 2 yrs · Bengaluru Area, India

  • As a part of acquisition of Broadcom's IOT team
VerilogWIFI Design

Broadcom

Engineer Staff 1

Jul 2015 – Jun 2016 · 11 mos · Bangalore

  • Got familiar with standard 802.11 a/b/n/ac/ax/p,
  • Worked on wireless 802.11 MAC low power design,
  • Worked on PALLADIUM quickturn emulation,
  • Worked in Wifi chip DV team
VerilogWireless Communication

Vitesse semiconductor is now microsemi

Intern Design Engineer

Jan 2015 – Jun 2015 · 5 mos · Hyderabad

  • #Ethernet COntroller
Verilog

Rci drdo

Intern

May 2014 – Jul 2014 · 2 mos · Hyderabad

  • Implementation of AFDX End system in Verilog
Verilog

Education

International Institute of Information Technology Hyderabad (IIITH)

Master of Technology - MTech — VLSI and Computer engineering

Aug 2013 – Present

International Institute of Information Technology Hyderabad (IIITH)

Master of Technology (M.Tech.) — VLSI and CE

Jan 2013 – Jan 2015

Ramaiah Institute Of Technology

B.E — Electronics and Communication

Jan 2009 – Jan 2013

Stackforce found 58 more professionals with Vlsi Design & Rtl Development

Explore similar profiles based on matching skills and experience

Aditya Verma

Aditya Verma

Senior Lead Engineer

at Qualcomm

Bengaluru, India7 yrs 6 mos exp
DK

Dr. Vandana Khanna

Dy dean (PhD)

at The NorthCap University

Gurgaon, India22 yrs 9 mos exp
SRI RAMA KRISHNA KAUSHIK VARANASI

SRI RAMA KRISHNA KAUSHIK VARANASI

Senior Design Engineer 1

at Microchip Technology Inc.

Hyderabad, India8 yrs 5 mos exp
Complex Programmable Logic Device (CPLD)Coverage Analysis
Shanthini Meganathan

Shanthini Meganathan

Human Resources Trainee

at EC Group International

Chennai, India2 yrs 11 mos exp
BK

Bhaskar Khandelwal

Bengaluru, India7 yrs exp
Low-Power DesignPower AnalysisPower Optimization
Ankur Shukla

Ankur Shukla

Senior Staff Engineer

at Qualcomm

Noida, India12 yrs 9 mos exp
Pravin Bagul

Pravin Bagul

Senior Staff Engineer

at Synopsys Inc

Pune, India8 yrs 5 mos exp
ASIC DesignRTL DesignCDCLint
RM

Raghava Madem

Staff R&D Engineer

at IBM

Bengaluru, India4 yrs 6 mos exp
Low Power VLSI DesignRTL Design