Ajo Robits — Software Engineer
knowledge in SystemVerilog Very good knowledge in verification methodologies(UVM) Experience in using industry standard EDA tools for the front-end design and verification
Stackforce AI infers this person is a Design Verification Engineer with expertise in VLSI and digital electronics.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 10 mos
Skills
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in Universal Verification Methodology (UVM)
- Proficient in SystemVerilog and EDA tools
- Strong background in digital electronics and FPGA design
Work Experience
Tessolve
Design Verification Engineer (3 yrs 10 mos)
Capgemini Engineering
Associate Consultant (3 yrs 1 mo)
Dexcel Electronics Designs Pvt. Ltd
FPGA Engineer( RTL design) (1 yr 10 mos)
Education
Master of Engineering at Coimbatore Institute of Engineering and Technology
Bachler of Engineering at DMI College of Engineering, Anna University
