Nitin Lulani

Software Engineer

Bengaluru, Karnataka, India24 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

18+ years in SoC architecture and design.
Expert in complex server CPU and mobile chipset designs.
Proven leadership in global team collaboration.

Stackforce AI infers this person is a Semiconductor and EDA expert with extensive experience in SoC architecture and design.

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Skills

Core Skills

System On A Chip (soc)Rtl DevelopmentArchitectural DesignStatic Timing AnalysisDigital Designs

Other Skills

LintRTL CodingDesign ReviewCDCApplication-Specific Integrated Circuits (ASIC)SpyglassSystems DesignLow-power DesignAPBQuestaSimAMBA AHBAXIVHDLVerilogSynplify Pro

About

18+ years of diverse experience in frontend domains across various industries, including Xeon CPU SoCs, LTE/5G SoCs, MCU32 SoCs, EDA, and FPGA design; Expertise in SoC Debug, Security & Reset/Boot domains for complex Server CPU, Mobile chipset, MCU32 ASIC designs, Strong hold on Industry standard debug technologies for SoCs architecture – Intel Trace/Trigger, VISA, run control; ARM CoreSight Intel Server Security architecture - FW patching/authorization, Secure boot, DFx security, Config access control; Fuse security; Authorized debug flows Strong leadership experience in driving IP/SoC RTL/coding/architecture/micro-arch/QC/debugging FE design exposure to advanced tech nodes - Intel 18A, Intel 3/4, 10nm,14nm, 28nm and TSMC 7nm process nodes Extensive experience with interfaces/protocols - AMBA AXI/AHB/APB/Low Power Interfaces(Q-ch), DMA, JTAG, MIPI debug for I3C, VME bus protocol, I2C, SPI, OCP, DDR3/DDR4 MIG controllers (Virtex7), high speed SerDes (Altera PHYLite, LVDS), transceivers etc. Proven track record of working efficiently with teams across the globe.

Experience

Intel corporation

4 roles

Principal Engineer, SoC Architecture

Promoted

Jul 2025 – Present · 8 mos

Technical Lead

Promoted

Nov 2021 – Present · 4 yrs 4 mos

Silicon Architecture Engineer

Jul 2019 – Present · 6 yrs 8 mos

LintSystem on a Chip (SoC)RTL CodingDigital DesignsDesign ReviewCDC+5

Member Of Technical Staff

Jul 2018 – Jul 2019 · 1 yr

Trace & Debug IP design for Intel Modem, Trace NoC design

LintSystem on a Chip (SoC)RTL CodingDigital DesignsDesign ReviewCDC+6

Microchip technology inc.

Principal Design Engineer

Sep 2017 – Jul 2018 · 10 mos · Bengaluru Area, India

Micro architectural design of complex IP macro blocks for 32-bit Microcontroller SoC,
Expertise in Front end design flows - RTL Synthesis, Simulation, Lint, CDC, STA, logic optimization/debug, AMBA5 AHB, AXI, APB bus interface design, SystemVerilog, etc.

LintSystem on a Chip (SoC)RTL CodingDigital DesignsDesign ReviewCDC+10

Synopsys inc

3 roles

Sr-II. R&D Engineer (IP development)

May 2016 – Aug 2017 · 1 yr 3 mos

Design & develop debug IPs for Synopsys' Identify FPGA debugger tool
HAPs70, HAPs80 platform based FPGA prototyping & debugging flow

LintStatic Timing AnalysisRTL CodingDigital DesignsDesign ReviewCDC+7

Sr-II. CAE

May 2015 – Apr 2016 · 11 mos

Lead CAE for Synplify Pro/Premier mapper for Altera FPGAs.

LintStatic Timing AnalysisRTL CodingDigital DesignsCDCRTL Development+3

Sr-I. CAE

Oct 2011 – Apr 2015 · 3 yrs 6 mos

Technical lead for validation & testing feature synthesis support for Synplify tools (Pro/Premier) - Altera, Lattice, SiliconBlue mappers.
Skills:
EDA, HDL and RTL Synthesis Tool validation, FPGA Architecture and FPGA Technology Mapper validation, Logic Synthesis, testbench development, Hardware Design & Verification, logic equivalence checking, Verilog, VHDL, Linux (Shell scripting), Synplify tools, VCS, Aldec-Riviera, Modelsim, Altera- Quartus, Xilinx ISE, Lattice Diamond, DC, PT, Matlab, Aldec-Riviera

LintStatic Timing AnalysisRTL CodingDigital DesignsCDCRTL Development+3

Raja ramanna centre for advanced technology (rrcat)

4 roles

Scientific Officer E

Jul 2010 – Dec 2011 · 1 yr 5 mos · Greater Indore Area

Worked for 7+ years at RRCAT Indore.
Fully owned the development, testing and commissioning of FPGA based VME IO boards for timing control systems (with resolutions in the range of sub-nano seconds) for Indus-2 control system. These developments helped to achieve critical targets (https://inis.iaea.org/search/searchsinglerecord.aspx?recordsFor=SingleRecord&RN=46028334). Also contributed for the development and commissioning of Orbit correction package for Indus-2 particle accelerator.
Specialties -
Microarchitectural design, RTL, Verilog/VHDL Coding for design & testbench verification – delay generation logic, coincidence logic, FIFO controller, I2C, SPI interface, VME Bus protocol etc.
Designed multilayer PCB schematics for FPGA based VME form factor boards
Developed MATLAB based solutions for Indus-2 Orbit Correction

RTL CodingDigital DesignsRTL DevelopmentSystems Design