Anshul Kumar

Product Engineer

San Diego, California, United States22 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in EDA verification and software architecture.
  • Proven track record in managing complex FPGA projects.
  • Strong mentorship and team leadership skills.
Stackforce AI infers this person is a highly skilled EDA verification architect with extensive experience in FPGA and software development.

Contact

LinkedIn

Skills

Core Skills

FpgaFormal Verification

Other Skills

QoRClock Tree SynthesisRuntimeDebuggingSoftware EngineeringPerlVHDLVerilogVLSIData StructuresCVSMultithreadingASICClearCaseLinux

About

A technical architect in the EDA verification R&D field, I have been involved in the architecture and development of large-scale software systems for class-leading products. I have extensive experience in software architecture, implementation, and customer rollout. Specialties: -STL, Data structure, BGL and Boost -Customer Evaluation -Formal Verification -Greenfield project -Technical project management -Technical interview process of R&D candidates Language: C, C++, Shell Programming and Perl Tool: Google Profiler, GDB, Google Test and Coverity

Experience

Siemens digital industries software

Architect

Jan 2026 – Present · 2 mos · San Diego, California, United States

Synopsys inc

Principal Engineer

May 2015 – Jan 2026 · 10 yrs 8 mos · San Diego, California, United States · On-site

  • Managed QoR for the synthesis engine of the HAPs FPGA verification platform
  • Worked and managed the gated clock conversion
  • Architected and developed functional connectivity extraction on SOC designs
  • Lead technical development of class-leading connectivity application based on formal methods
  • Working on clock information propagation
  • Mentorship, code review and induction of new members of the team
FPGAQoRClock Tree SynthesisRuntimeFormal Verification

Mentor graphics

Member of Consulting Staff

Aug 2014 – May 2015 · 9 mos · Noida, Uttar Pradesh, India

  • Worked on the improvement of synthesis run times for Tessent (DFT) product platform
  • Designed and implemented back-referencing information flow throughout the Tessent platform

Atrenta

Consulting Engineer

Jan 2006 – Aug 2014 · 8 yrs 7 mos

  • Worked on the formal engine interface for supporting a parallel computing system
  • Managed and implemented a new clock to clock verification
  • Worked on structural abstraction
  • Worked on techniques for improving SAT and BDD runtimes
  • Worked on property modeling for formal verification

Computer associates

Engineer

Mar 2005 – Mar 2006 · 1 yr

  • Was working on the Storage Management solution from CA

Cadence design systems

S/W engineer

Jun 2003 – Mar 2005 · 1 yr 9 mos

  • Under took BlackTie to IFV comparison study
  • I received an award for the effort from the Group Director.
  • Mixed-Language & VHDL single verb invocation utilities for IFV

Education

Doctor Bhim Rao Ambedkar University

B.E. — Computer Science and engineering

Jan 1999 – Jan 2003

City montessori

ISC

Jan 1996 – Jan 1998

St. Joseph college

ICSC

Jan 1991 – Jan 1996

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