Ayushi Jain

Software Engineer

Bengaluru, Karnataka, India9 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expert in RTL Development and VLSI Engineering.
  • Proficient in Verilog and VHDL for circuit design.
  • Experience with FPGA and PCIe subsystem design.
Stackforce AI infers this person is a VLSI Engineer specializing in RTL design and FPGA development.

Contact

LinkedIn

Skills

Core Skills

Rtl Development

Other Skills

AlgorithmsCC++Digital Signal ProcessingField-Programmable Gate Arrays (FPGA)MatlabPCIeSTMVHDLVLSI EngineeringVerilog

Experience

D-matrix

Staff Engineer

Sep 2025 – Present · 6 mos · Bengaluru, Karnataka, India · Hybrid

Qualcomm

3 roles

Senior Lead Engineer

Dec 2023 – Sep 2025 · 1 yr 9 mos

Senior Engineer

Promoted

Nov 2020 – Dec 2023 · 3 yrs 1 mo

  • RTL Design
RTL Development

Engineer

Mar 2018 – Nov 2020 · 2 yrs 8 mos

  • RTL Design
RTL Development

Intel corporation

PCIE subsystem Design(contingent employee)

Jun 2017 – Dec 2017 · 6 mos · Bengaluru, Karnataka, India

Logic-fruit technologies

R & D Engineer (FPGA Dep.)

Jun 2016 – Feb 2018 · 1 yr 8 mos · Bengaluru, Karnataka, India

Drdo, centre for airborne systems

Internship

Jun 2015 – Jul 2015 · 1 mo · Dehradun

  • Implementation of Deblurring Algorithm under Super Resolution

Education

Motilal Nehru National Institute Of Technology

Bachelor’s Degree — Electronics and Communications Engineering

Jan 2012 – Jan 2016

St. Joseph's Co-Ed School

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