Apr 2019 – Dec 2023 · 4 yrs 8 mos · India · On-site

• Project:
• Error Handling IP for Gen3(IEH) and Gen4(RAS):
• 1. Handling of registers in OS-XML
• 2. RTLGen using OS studio.
• 3. Defined MAS for packet transaction in gen4.
• 4. RTL for Treg collector block which does reg read and write.
• 5. Developed tmsg collector block for input pkt transaction.
• 6. FSM for sending out pkt to all other blocks.
• 7. Designed reg wrapper block.
• 8. Developed Time sync and ierr ( fatal error) block.
• Project: DFIVR
• 1. Designed DAC INL correction block.
• 2. RTL for ipsg block.
• 3. Front end tool run.
• Project: CRC feature for I2C IP
• 1. Designed and verified CRC feature during write mode.

Jan 2018 – Mar 2019 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

• Project: MIPI I3C Slave IP, Addressable SPI Slave
• Responsibilities:
• Defined specification of slave as per standard MIPI I3C.
• Developed RTL using Verilog, Verified using Questasim & Synthesized using Synopsys Design Compiler.
• Project: R8051XC2 SOC Power Sequence
• Responsibilities:
• Designed Start Up FSM and APC (Analog Power Control) Initialization FSM.
• Developed RTL code using Verilog, Verified using Simvision & Synthesized using Genus.

Jun 2017 – Dec 2017 · 6 mos · Bengaluru, Karnataka, India · On-site

• Project: Router 1X3, SPI Verification
• Responsibilities:
• Completed the study of the router & SPI protocol.
• Designed RTL in Verilog using Xilinx ISE, Verified using Rivera Pro.
• Implemented the class based verification environment in UVM.