Apr 2020 – Dec 2022 · 2 yrs 8 mos · Austin, Texas, United States

• Bring up, stress test and deliver on performance on emulation platform to spec for the next generation ML SoC; run HW focused stress tests and interface w/ SW team to ensure successful performance of SW workloads and utilization of HW
• Responsible for simulation, emulation, formal verification, design automation & verification methodology
• Plan, execute and lead a strong team of engineers to successful functional closure and various milestones leading to RTL freeze and successful TO
• Responsible for fabric deadlock verification (planning and execution), various aspects of chip functionality
• DV manager (1:1s, hiring, team performance/assessments, vendor relation)
• Delivered on fully functional A0 silicon for Trainium SoC (best performing deep learning chip on the cloud); https://aws.amazon.com/machine-learning/trainium/

Nov 2011 – Apr 2020 · 8 yrs 5 mos · Austin, Texas Metropolitan Area

• Verification Lead for ARM V8 CPU Cores in Austin
• Cortex A77
• https://www.anandtech.com/show/14384/arm-announces-cortexa77-cpu-ip
• Cortex A72
• http://www.arm.com/products/processors/cortex-a/cortex-a72-processor.php
• Cortex A57
• http://www.arm.com/products/processors/cortex-a/cortex-a57-processor.php
• AMBA 5 CHI
• http://www.arm.com/about/newsroom/arm-announces-amba-5-chi-specification-to-enable-high-performance-highly-scalable-system-on-chip.php
• CCN-504
• http://www.arm.com/about/newsroom/arm-announces-new-high-performance-system-ip-to-address-demand-for-energy-efficient-many-core.php

Mar 2006 – Nov 2011 · 5 yrs 8 mos · Austin, Texas

• Responsible for verifying the control unit of a microprocessor. Involved in all aspects of verification - planning, task assignment, constrained-random stimulus, checkers, integration with the core, functional coverage implementation and closure. Designed the unit for easy core level migration. Used System Verilog/OVM & assertions.
• Developed a comprehensive memory checker that verifies all the caches and memories in the core against the reference model. This checker has comprehensive understanding of various levels of caches, memories, keeps track of snoop activity etc.
• Verified a DSP CPU at the core and SoC level. This includes leading a team of 6 engineers in three different time zones, schedule tracking, delivery responsibility
• VMM to OVM migration of SV code
• Responsible for creating a template for ViP for PHY designs

Jan 2005 – Mar 2006 · 1 yr 2 mos · Austin, Texas

• Developed complete Vera based testbench architecture from scratch for a brand new product. This included developing reusable components for stimulus generation, checking, reporting and general utilities (drivers, monitors, checkers, generators, functional coverage) - Verified an audio codec (both block-level and reuse at System-level). Blocks included industry standard I2S in various flavors.
• Introduced new verification techniques (Vera RVM & OOP) and assertion-based verification.
• Created & maintained build, simulation and regression infrastructure (using OO Perl)
• Developed a web-based scheme to monitor regressions. This was done using Apache and running Perl/CGI scripts on the backend. Integrated functional & code coverage reports into this scheme

Jun 1998 – Dec 2004 · 6 yrs 6 mos · Austin, Texas

• Responsible for development, support and release of internal RVM like base classes across various product groups for entire Freescale. - Responsible for advocating formal & semi-formal verification techniques in verification.
• Responsible for evaluating vendor tools for formal verification.
• Involved in the development and deployment of System Verilog assertions across the company.
• Helped with training modules intended to make users familiar with the usage and advantages of assertions.
• Worked on a pilot project for a processor core to help drive the usage of assertion-based verification techniques – specifically property/model checking
• Responsible for developing, supporting and releasing an RTL to custom gate netlist generator for internal use across the company.
• Responsible for developing a verilog compiler, parser.
• Responsible for developing and maintaining a web-based regression flow that helped