Ritesh Kumar Tiwari — Product Engineer
Looking to pursue a challenging career in the VLSI field and getting familiar with current technology, thus enhancing my knowledge and skills and complementing the company’s growth. Tools and Languages: HDL: Verilog (Xilinx Vivado) Simulation Tool: LTspice Synthesis Tool: RTL Compiler DRC/LVS Tool: Virtuoso (Cadence) Programming Skills: C Technical Skills: •Familiar with the ASIC design flow from RTL to GDS-II, RTL Coding & Design, Static timing analysis(STA)
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in ASIC design and verification methodologies.
Location: Allahabad, Uttar Pradesh, India
Experience: 4 yrs
Career Highlights
- Expertise in VLSI and ASIC design flow.
- Proficient in multiple HDL and simulation tools.
- Strong foundation in verification methodologies.
Work Experience
Cadence Design Systems
Verification Engineer 2 ( Emulation Engineer ) (2 yrs 4 mos)
Verification Engineer 1 (9 mos)
Arm
Consultant (CPU Architecture Verification) (11 mos)
Education
M.Tech at Indian Institute Of Information Technology Allahabad
Bachelor of Technology - BTech at University of Allahabad