Jan 2024 – Dec 2025 · 1 yr 11 mos · Noida, Uttar Pradesh, India · Hybrid

• Owned and led the end-to-end development of I3C transactor IP, from micro-architecture to emulation, across multiple customer use cases.
• Designed and developed micro-architecture and RTL for I3C Controller and Target blocks, based on full I3C v1.0 spec and selectively integrating key features from v1.1.1.
• Implemented I3C specific logic for arbitration, dynamic addressing, high data rate modes, interrupts, I2C backward compatibility and several other protocol defined features.
• Collaborated with internal teams and customers to incorporate feature requests, debug field-reported scenarios, and resolve corner-case bugs at design level.
• Optimized Controller and Target RTL to ensure timing closure and meet area and performance requirements for the Strato CS Hardware.
• Designed a TCP/IP socket-based interface for the I3C IP to send/receive bus transactions—bypassing the traditional testbench for transaction scheduling and response.
• Performed sanity validation of designed features by authoring tests in SystemVerilog/SystemC. Also tested the design on Veloce Emulator.
• Provided technical mentorship to new team members onboarding to the I3C IP.
• Authored architecture specs, detailed implementation documents, test plans and customer specific feature proposals.
• Also contributed to USB 3.1 transactor IP by implementing configurable device descriptor logic to support user-defined configurations.

Dec 2021 – Jan 2024 · 2 yrs 1 mo · Noida, Uttar Pradesh, India · Hybrid

Sep 2020 – Dec 2021 · 1 yr 3 mos · Gurugram, Haryana, India

• Worked on the design of a PCIe Analyzer capable of capturing and analyzing traffic over sixteen lanes and up to Gen5 speeds.
• Owned micro-architecture and implementation of the Packet Decoder Block, responsible for ensuring precise and efficient data processing.
• Developed RTL modules for Ordered set detection, OS compression, TLP/DLLP detection and marking, and lane combining logic.
• Conducted design synthesis using Xilinx Vivado. Implemented RTL optimizations to achieve timing closure and ensure area efficiency. Also performed CDC checks at required places to ensure safe signal transfer.
• Performed sanity verification of Packet Decoder Block and the overall Analyzer Design by developing test scenarios to validate functionality and adherence to specification.
• Created BitFiles and performed on-board validation on FPGA, debugging functional mismatches and traffic decode issues.

Sep 2019 – Sep 2020 · 1 yr · Gurugram, Haryana, India

Jul 2019 – Mar 2020 · 8 mos · Remote

• Learned Verilog and SystemVerilog syntax along with RTL design fundamentals and core verification concepts.
• Worked on multiple design and verification projects, including RTL Design of a FIFO buffer, functional verification of a memory controller and an AXI 3.0 interconnect.
• Developed basic working knowledge of AXI 3.0 protocol through project work.

Jun 2018 – Aug 2018 · 2 mos · Dahej, Gujarat, India

• Studied the working of Centrifugal Compressors, mainly C2R and C3R compressors, as a part of my summer internship project. These compressors are currently being used for refrigeration purposes at Reliance Industries Ltd Dahej Manufacturing Division (RIL- DMD). The refrigerants produced by these compressors are ethylene and propylene in liquid phase.
• Put together the data related to previous trips/ failures experienced in these compressors at DMD in the past and analyzed the same.
• On the basis of analysis of failures, published recommendation from Instrumentation perspective, suggesting improvements in efficiency and minimization of tripping and failure incidents in the future.

May 2017 – Jul 2017 · 2 mos · Chandigarh, Chandigarh, India

• Attended the VLSI Design and FPGA Implementation course as a Summer Trainee.
• Got exposure to concepts of Digital Design, ASIC Design Flow and hands on experience in VHDL programming. Towards the end of my training, I developed and tested the design for a Vending machine using VHDL programming on Xilinx ISE, and finally implemented the design on an FPGA

Oct 2015 – Jan 2018 · 2 yrs 3 mos

• Worked as an Online Tutor, providing help to students in the areas of Physics, Chemistry and Mathematics and Economics. Hand-picked through a rigorous testing process, tutors were selected at a topic-level to ensure the best fit for the student, unlike coaching centers where the same professors usually cover all topics within a subject.