Gnana Kanagaratnam

CEO

Portland, Oregon, United States25 yrs 9 mos experience

Highly Stable

Key Highlights

20 years of expertise in EDA and IC design.
Proven track record in technical sales strategies.
Leadership in building high-performing sales engineering teams.

Stackforce AI infers this person is a leader in EDA and IC design solutions with extensive technical sales experience.

Contact

Skills

Core Skills

Physical VerificationSales EngineeringLow-power DesignPhysical DesignEda

Other Skills

Calibre designverification solutionssales strategiestechnical campaignslow-power design methodologiesrouting/timing closuredesign planningtechnical evaluationbenchmark campaignsplace-and-route technologiesTCLASICStatic Timing AnalysisTiming ClosureSoC

About

Technical sales leader and EDA IC Design Technologist with proven-track record of success in delivering EDA solutions to strategic customers, building top class sales engineering teams and successfully creating and executing technical sales strategies. Strong technical background through over 20 years of technical sales and customer success expertise in EDA domain, focused on all aspects from netlist through GDS flows and best-in-class chip performance, power and area. Expertise in Calibre design and physical verification solutions.

Experience

Synopsys inc

Executive Director, Product Management

Nov 2025 – Present · 4 mos · Hillsboro, Oregon, United States

Siemens eda (siemens digital industries software)

2 roles

Global Technical Director – Digital Design Creation (RTL-to-GDS)

Jan 2025 – Oct 2025 · 9 mos · Portland, OR

Technology Solutions Director – Calibre Design-to-Silicon & Digital Design (RTL-to-GDS)

Sep 2019 – Dec 2024 · 5 yrs 3 mos · Portland, OR

Mentor graphics

2 roles

Senior Manager - Calibre Design-to-Silicon & Digital Design (P&R)

May 2012 – Sep 2019 · 7 yrs 4 mos

Lead the Calibre design and verification solutions group in World-Trade Americas region; Drove Calibre core sign-off and advanced technologies in the IC customer base encompassed of strategic, key and regional sales channels; Collaborated with area sales to create selling strategies and execute technical campaigns to win and grow physical verification business.
Previously managed the place-and-route product specialists team and concurrently served as individual contributor for mission-critical technical campaigns related to Mentor's IC design solutions products; Lead multiple technical campaigns and mission-critical customer engagements in key accounts that resulted in business wins and tape-out successes.

Calibre designverification solutionssales strategiestechnical campaignsPhysical VerificationSales Engineering

Technical Lead

Dec 2008 – May 2012 · 3 yrs 5 mos

Technical lead focused on technical benchmark/evaluation through successful deployment of Mentor's Olympus place-and-route platform and customer engagement management; Specialities include low-power design methodologies, routing/timing closure, design planning of complex SoC designs and leading business-critical/high risk engagements with the goal of delivering results.

low-power design methodologiesrouting/timing closuredesign planningLow-power DesignPhysical Design

Magma design automation

2 roles

Technical Lead

Promoted

May 2006 – Dec 2008 · 2 yrs 7 mos · San Francisco Bay Area

Strategic accounts technical lead focused on driving technical evalution/benchmark campaigns, adoption and proliferation of Magma Blast/Talus based place-and-route technologies; Drove netlist-to-silicon flow solutions through successful tape-outs of numerous broadband, STB, wireless, DVT and network switch class SoCs

technical evaluationbenchmark campaignsplace-and-route technologiesPhysical DesignEDA

Senior Product Engineer

Apr 2004 – May 2006 · 2 yrs 1 mo · San Francisco Bay Area

Product engineering solutions methodologist/architect for Magma's next generation design planning and prototyping platform (Blast Plan Pro) for SoC designs

Monterey design systems, inc.

Senior Applications Engineer

Apr 2001 – Apr 2004 · 3 yrs · San Francisco Bay Area

Monterey was acquired by Synopsys **
Solutions architect focused on next generation hierarchical flows/methodologies for complex high-capacity SoC application platforms, networking, digital video decoder and STB chips; Lead competitive replacement and benchmark/evaluation campaigns across Americas, PacRim and Japan regions

Aristo technology, inc.

Applications Engineer

May 2000 – Apr 2001 · 11 mos · San Francisco Bay Area

Aristo was acquired by Monterey Design Systems, Inc. **
Methodology architect for hierarchical SoC designs using Aristo's IC Wizard chip planning platform; Drove product introduction and first competitive benchmark win at a major ASIC customer in Japan; Lead numerous successful customer engagements that lead to business wins across Japan and Americas regions.