Dr. Rajesh Navandar (PhD in VLSI) — CEO

Career Objective: To work in VLSI Domain where performance is rewarded with new responsibilities with knowledgeable environment and to grow along with the organization as a core member of the same. Physical Design STA (Netlist - Floor Planning - Partitioning - Placement - Clock-tree Synthesis - Routing - Design Verification - GDSII) with exp using the latest PD tools, Synopsys (ICC/IC Compiler, PrimeTime),Areas of expertise includes Library Preparation, Floor planning, IO Ring creation, Power Planning, Placement , CTS and Routing activities, Formal Verification, Timing Closure, Static and Dynamic power EM/IR analysis, Signal EM and Crosstalk noise analysis and Physical Verification, Low power design techniques and Physical Design Flow and methodology Netlist - GDS2 Block/Chip level Synthesis, Static Timing Analysis, Floorplan, Placement, CTS, Routing,ECO, DFM, DRC, LVS, Extraction, Schematic, Layout, RTL 2 GDSII, Floor and power planning Placement and routing IR, Power and timing analysis Clock tree synthesis Skew minimization Signal integrity ( EM) fix and analysis Static timing analysis (STA) DFM – redundant vias, metal density Layout – chip finishing Physical verification – DRC/LVS Experienced in floorplaning, placement ,clock tree synthesis, optimization for timing closure,power distribution planning and routing at block level. Knowledge of static timing analysis concepts for both block level and top-level. Strong knowledge in signal integrity issues such cross-talk, EM and IR drop. Working knowledge of low power methodologies and impact on overall design goals. Knowledge of post layout physical verification and DFM rules. Specialties: CMOS ASIC Design , , CMOS Circuit Design, ASIC Physical Design. Good Knowledge of ASIC flow (RTL to GDSII). •In-depth understanding of RTL design (Verilog), Verification, Synthesis, Static Timing Analysis, Floorplan, Placement, CTS, Routing, DFM, DRC, LVS,

Stackforce AI infers this person is a VLSI Design expert specializing in ASIC Physical Design and low power methodologies.

Location: Pune, Maharashtra, India

Experience: 1 yr 9 mos