Laxmi Pathi

Product Manager

Bengaluru, Karnataka, India17 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expertise in Physical Design and Timing Closure.
  • Strong background in RTL coding and EDA tools.
  • Proven track record in the semiconductors industry.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and RTL methodologies.

Contact

LinkedIn

Skills

Core Skills

Physical DesignSoc Design

Other Skills

PnRTiming ClosureDesign Rule Checking (DRC)CMOSEDARTL CodingRTLSynthesis and STAStatic Timing AnalysisLow-power DesignVerilogVLSILogic SynthesisSimulationsVHDL

About

Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Strong engineering professional skilled in PnR ,Timing Closure, Design Rule Checking (DRC), CMOS, EDA, and RTL Coding.

Experience

17 yrs 5 mos
Total Experience
2 yrs 10 mos
Average Tenure
8 yrs 11 mos
Current Experience

Intel corporation

SoC Design Engineer(PnR)

Jun 2017 – Present · 8 yrs 11 mos · Bangalore

PnRTiming ClosureDesign Rule Checking (DRC)CMOSEDARTL Coding+2

Wipro limited

Senior Software Engineer

Jun 2016 – Jun 2017 · 1 yr · Bangalore

  • SoC Design Engineer

Samsung r&d institute india - bangalore private limited

Technical Lead

Dec 2014 – Jun 2016 · 1 yr 6 mos · Bangaon, West Bengal, India

  • RTL2GDSII

Tata elxsi

Specialist (P&R)

Aug 2013 – Nov 2014 · 1 yr 3 mos · Greater Bengaluru Area

Interra systems

Senior Engineer

Apr 2012 – Dec 2012 · 8 mos · Greater Bengaluru Area

Magma design automation pvt bangalore

MTS

Mar 2008 – Apr 2012 · 4 yrs 1 mo · Greater Bengaluru Area

Education

Indian Institute of Technology, Kharagpur

M.Tech — Microelactronics&VLSI

Jan 2004 – Jan 2006

Acharya Nagarjuna University

Jan 1999 – Jan 2002

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