Divya Gupta

Software Engineer

New Delhi, Delhi, India12 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in Static Timing Analysis and Physical Design.
  • Proven track record in high-speed digital design.
  • Strong background in semiconductor engineering.
Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on Physical Design and Timing Analysis.

Contact

Skills

Core Skills

Static Timing AnalysisPhysical DesignHigh-speed Digital Design

Other Skills

ARMASICAlgorithmsAnalogAutomation in STACC++CadenceDRCDebuggingECOEDAEmbedded Applications using MicroncontrollersEmbedded SystemsFPGA

Experience

7rays semiconductors india private limited

Senior Staff Engineer

Mar 2025Present · 1 yr · Noida, Uttar Pradesh, India · On-site

Qualcomm

2 roles

Lead Senior Physical Design Engineer

Promoted

Jan 2022Mar 2025 · 3 yrs 2 mos · On-site

  • 1. Leading timing closure activities for multiple blocks for high speed CPUSS in 4nm process across >300 corners.
  • 2. Constraints co-relation across sub-system level and SoC level runs.
  • 3. DCD and Aging DCD signoff.
Static Timing AnalysisPhysical DesignAutomation in STAECO

Senior Physical Design Engineer

Aug 2017Dec 2021 · 4 yrs 4 mos · On-site

  • Timing Closure for 3+ GHz CPUs in 7nm and 4nm process across >300 corners.
High-speed Digital DesignPlace & RouteTcl-TkStatic Timing AnalysisPrimetimetempus+1

Apple

Intern

May 2016Aug 2016 · 3 mos · Cupertino · On-site

  • 1. Reducing LSF resources while running leakage optimization for multi-mode CPU blocks.

Arm

Grade III Design Engineer

Jul 2014Jul 2015 · 1 yr · Bangalore

  • Worked on test chips in 16nm FinFET process
  • 1) Ownership of STA flow (using PrimeTime), complete automation and deployment across multiple design teams.
  • 2) Ownership of PV (using Mentor Calibre and Cadence Litho Physical Analyzer, Cadence CMP Predictor) , complete automation and deployment across multiple design teams.

Texas instruments

2 roles

Senior Design Engineer

Feb 2014Jun 2014 · 4 mos

  • Worked on Silicon revisions of legacy micro-controllers.

Design Engineer

Jul 2011Jan 2014 · 2 yrs 6 mos

  • Involved in complete placement to GDS flow for ARM cores at 65nm technology for automotive micro-controllers.
  • Performed custom routing for analog macros to mitigate IR drop and address stringent resistance requirements for Flash macros
  • Involved in timing closure at the SoC level
  • Involved in Static Timing Analysis of TI's benchmark multi-application processors called OMAP (Open Multimedia Application Platform ) at sub-chip level as well as SoC level.
  • Well versed with STA for SoCs having multiple voltage islands at 28nm & 45nm technology nodes.
  • Experienced in analyzing the effect of AOCV on timing.
  • Adept at automating STA regressions using crontab, makefiles and scripting in Perl Shell & Tcl.
  • Skilled in correlation activity for tool evaluation process.

Defence research and development organisation

Intern

May 2010Jun 2010 · 1 mo · New Delhi Area, India

  • Created a Thermo Electric Cooling system using PIC microcontrollers

Defense research & development organization

Intern

Jun 2009Jul 2009 · 1 mo · New Delhi Area, India

  • Created a Low Frequency Waveform Generator using 8051 microcontrollers

Education

North Carolina State University

Master’s Degree — Computer Engineering

Jan 2015Jan 2017

Netaji Subhas Institute of Technology

Bachelors in Enggineering — Electronics & Communcation

Jan 2007Jan 2011

The Mother's International School

Apr 1997Mar 2007

Greenfields Public School

Apr 1995Mar 1997

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