Gaurav Sharma

Software Engineer

Greater Delhi, Delhi, India10 mos experience

Key Highlights

Expert in UVM and SystemVerilog for design verification.
GATE Qualified with top 5% ranking in NPTEL certifications.
Hands-on experience in building robust verification environments.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in design verification methodologies.

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Skills

Core Skills

Design VerificationUvm Testbench Development

Other Skills

Universal Verification Methodology (UVM)SystemVerilogProblem SolvingSystemVerilog Assertions (SVA)Cadence XceliumSystem Verilog assertionsFunctional VerificationRTL VerificationAssertion Based VerificationFormal VerificationCode CoverageAMBA AHBCadence SoftwareSystem on a Chip (SoC)Phase-Locked Loop (PLL)

About

I am currently part of the SoC verification team at STMicroelectronics. Previously, during my internship at STMicroelectronics, I worked on IP and subsystem-level verification. Core Expertise 🔹 Design Verification (IP / Subsystem / SoC) 🔹 UVM Testbench Development 🔹 SystemVerilog & SVA 🔹 Functional Coverage & Scoreboarding 🔹 Cadence Xcelium Simulation & Debug 🔹 MBIST & MREPAIR Subsystem Verification I hold an M.Tech in VLSI Design from NIT Jalandhar, am GATE Qualified, and have completed multiple NPTEL certifications from IIT Kharagpur, including a national top 5% ranking. I am passionate about building robust verification environments using UVM, SystemVerilog, and SVA, with experience across IP, subsystem, and SoC verification. I am open to full-time opportunities in IP, subsystem, and SoC design verification with leading semiconductor companies.

Experience

Stmicroelectronics

Graduate Engineer

Nov 2025 – Present · 4 mos · India · Hybrid

SoC Verification

Universal Verification Methodology (UVM)SystemVerilogDesign VerificationUVM Testbench Development

Indian institute of technology, delhi

Research Scholar

Jul 2024 – Jan 2025 · 6 mos · Delhi, India · On-site

Problem Solving

Stmicroelectronics

Project Trainee

Jul 2023 – Jun 2024 · 11 mos · India · On-site

Verified MBIST and MREPAIR subsystems using UVM, SystemVerilog, and SystemVerilog Assertions (SVA).
✅ Built UVM-based testbench from scratch (driver, monitor, scoreboard, agent, environment).
✅ Developed assertions for protocol checks and integrated them into the environment.
✅ Performed simulation & debugging using Cadence Xcelium.
✅ Collaborated with the design team to define stimulus and expected results based on technical specifications.

Universal Verification Methodology (UVM)SystemVerilogDesign VerificationUVM Testbench Development