Nidhi Gupta

Product Engineer

Hillsboro, Oregon, United States13 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC design and SoC verification.
  • Achieved 100% functional coverage in multiple projects.
  • Strong background in UVM and RTL verification methodologies.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and SoC design.

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Skills

Core Skills

Soc VerificationUvm

Other Skills

AMBA AHBAPBARM ArchitectureAXIApplication-Specific Integrated Circuits (ASIC)Assembly LanguageC (Programming Language)C++Cache CoherencyCode CoverageCommunicationComputer ArchitectureComputer ArithmeticComputer HardwareConcurrent Programming

About

I’ve always been fascinated by how things work at a fundamental level—especially when it comes to technology. This curiosity led me down the path of becoming a verification engineer specializing in ASIC design and system-on-chip (SoC) verification. Currently pursuing my Master’s degree in Electrical & Computer Engineering at the University of Colorado Boulder has only deepened my passion for this field. During my time at Seagate Technology as both an intern and a member of the technical staff, I had the opportunity to dive into complex verification tasks involving various bus protocols like I2C and UART. I played a key role in debugging issues at the SoC level for HDD products which sharpened my analytical skills significantly. One of my proudest moments was implementing interrupt handling and tightly coupled memory accesses which streamlined our processes considerably. Before Seagate, I honed my skills at Samsung Electronics where I developed an IP verification plan for the TREX fabric involving 18 masters and 3 slaves. It was rewarding to see our team tackle challenges like low power states effectively while ensuring high functionality under various scenarios. My journey began as a junior engineer at nSys Design Systems where I developed test cases for USB 2.0 protocols—each step laid a strong foundation that continues to support my growth. Outside of work, I enjoy engaging with fellow tech enthusiasts through local meetups and hackathons where we can brainstorm innovative solutions together. Sharing knowledge is something I'm passionate about—it not only helps me grow but also creates a vibrant community around technology. If you're interested in discussing ASIC design or exploring collaboration opportunities within semiconductor engineering, feel free to reach out via email at nigu4232@colorado.edu Skills: System Verilog | UVM | Verilog | Python | C++ | Digital Electronics | SoC Verification | RTL Debugging | Functional Verification | Shell Scripting

Experience

Seagate technology

2 roles

VLSI Intern V | ASIC Verification, UVM Testbench Development, and RTL Verification

May 2024Jan 2025 · 8 mos · Longmont, Colorado, United States · Hybrid

  • * Programmed DDR4 memory with pre-load test-cases to estimate read efficiency and engineered LRDIMM test-bench

Member Of Technical Staff | SoC Verification, UVM Testbench Development, and RTL Simulation

Nov 2015Aug 2023 · 7 yrs 9 mos · Pune, Maharashtra, India · On-site

  • Accomplished 100% functional coverage and identified RTL defects by creating verification plans and UVM test-bench components for bus protocols (LLP, UART, SSI, I2C) at SOC level using constrained random verification
  • Implemented interrupt handling, TCM, ARM R8 processor, and PAD connectivity in a UVM based SOC test-bench
  • Improved RTL simulation accuracy by integrating a Verilog delay model into the existing workflow, achieving 100% functional coverage and streamlining test regressions for faster validation cycles in SOC design
  • Compiled weekly technical updates, enabling faster issue resolution through cross-geographic collaboration
  • Owned Gate-level simulation for all bus protocols.
UVM Testbench DevelopmentRTL SimulationSoC VerificationFunctional VerificationDebuggingUVM

Wipro limited

Senior Project Engineer | Verification, UVM Testbench Development, Functional Coverage Closure

Dec 2014Nov 2015 · 11 mos · Bengaluru, Karnataka, India · On-site

  • * Achieved 100% code coverage for AHB to APB bridge IP in Microchip's avionics project through UVM test-bench

Samsung electronics

Lead Engineer

Aug 2012Dec 2014 · 2 yrs 4 mos · Bengaluru Area, India · On-site

  • Engineered comprehensive specifications for an advanced UVM scoreboard, addressing over 15 RTL issues, including ID remapping challenges, to enhance verification processes
  • Demonstrated 95% code coverage as an owner of verification strategy and UVM test-bench for ODI IP from scratch

Nsys design systems

R&D Engineer - I

May 2010Jul 2012 · 2 yrs 2 mos · New Delhi Area, India · On-site

  • * Delivered OVM test-cases and driver component code enhancement for USB2 and MIPI protocol

Education

University of Colorado Boulder

Master's degree — Electrical and Computer Engineering

Aug 2023May 2025

Maharana Pratap College of Technology affiliated with R.G.P.V Bhopal, India

Bachelor of Engineering - BE — Electronics and Communication Engineering

Jun 2005Jun 2009

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