Aditi Lotlikar

Software Engineer

Bengaluru, Karnataka, India2 yrs 6 mos experience

AI ML PractitionerHighly Stable

Key Highlights

Achieved 64.8% error reduction in formal verification.
Led a 30+ member volunteer team at BITSAA Bangalore.
Transitioned into formal property verification with significant impact.

Stackforce AI infers this person is a Semiconductor and Telecommunications specialist with a focus on verification and design.

Contact

Skills

Core Skills

Formal Property VerificationDebuggingRtl DesignRtl VerificationResearch

Other Skills

SystemVerilogPeer MentoringSynopsys VCFormalTCLConnectivity VerificationClock Gating VerificationCadence VirtuosoFormal VerificationArtificial Intelligence (AI)JasperGoldWorkflow AutomationVerilogPython (Programming Language)Cross-functional CoordinationTechnical Writing

About

I’m a Formal Verification Engineer at AMD, working on AI GPUs - where I turn intricate logic into something you can trust, one property at a time. My current focus is Formal Property Verification, and I’ve been steadily expanding my depth across other formal applications. If there’s something to debug, refine or rethink, I’m usually the one quietly poking at it, persistently. I’m working toward a future in technical leadership, where I can drive not just silicon programs, but the systems and structures that help people grow. I'm especially excited about using AI to improve pre-silicon workflows and make technical excellence more scalable. In parallel, I lead Marketing and Events at BITSAA Bangalore - a space where I take end-to-end ownership of initiatives, build and manage a 30+ member volunteer team, and ensure smooth coordination across verticals. It’s a hands-on exercise in leadership, structure, and communication - skills I’m actively developing as I prepare to take on larger responsibilities at work in the future. When I'm not verifying logic, I find joy in curating newsletters, planning alumni events, and having conversations over filter coffee. If any of this resonates and you'd like to connect, I’m always up for a thoughtful conversation.

Experience

2 yrs 6 mos

Total Experience

2 yrs 6 mos

Average Tenure

2 yrs 6 mos

Current Experience

Amd

2 roles

Silicon Design Engineer 2

Dec 2024 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India · Hybrid

SystemVerilogPeer Mentoring

Silicon Design Engineer I

Sep 2023 – Nov 2024 · 1 yr 2 mos · Bengaluru, Karnataka, India · Hybrid

Formal X-Propagation Verification : Built TCL-based flows and ran formal X-Prop checks on Synopsys VC Formal, gaining a deep understanding of how the application leverages Sequential Equivalence Checking. Debugged extensively, uncovering multiple bugs and driving a 64.8% error reduction.
RAS Verification: Volunteered to take ownership of RAS verification when its scope was still undefined.
Learned the chip-wide RAS architecture (blocks, error-correction mechanisms, interactions).
Executed large-scale connectivity verification; Ensured reliable error reporting across the chip, with ~15 bugs identified in 2024 alone.
Maintained weekly regression checks post-March 2024, using evolving “Golden” CSVs to track design changes, detect missing connections, and report bugs early.
Formal Property Verification & Clock Gating: Transitioned into FPV, taking ownership of two design blocks.
Inherited blocks with basic end-to-end properties, then expanded them through weekly runs on revised design models - adding, refining, and pruning properties as designs evolved rapidly.
Improved convergence using abstraction techniques and boosted coverage by ~10% through new properties and debugging coverage runs.
Performed clock gating verification, uncovering 3–5 bugs per block, strengthening power-optimized design robustness.
Achieved 95–96% coverage before moving onto more critical tasks.
Mentorship (Jan–Dec 2024): Mentored two sets of interns across formal applications (X-Propagation, Connectivity Check, Clock Gating). Guided interns to ramp up quickly and contribute effectively - Enhancing my ability to teach, enable, and lead others in formal verification.

SystemVerilogSynopsys VCFormalFormal Property VerificationDebugging

Infinera

ASIC Design Engineering Intern

Feb 2023 – Sep 2023 · 7 mos · Bengaluru, Karnataka, India · Hybrid

Translated complex system requirements into robust RTL designs, contributing directly to ASIC development for next-gen optical networking systems.
Designed and implemented a Configurable TDM (Time Division Multiplexed) Generator that provided inputs for multiple circuits, delivering a ~60% improvement in efficiency and functionality across the project.
Developed and deployed a synchronous Alarms Module in TDM Data Clock Domain Crossing RTL Design, enabling early detection of erroneous output data.
Built 4 testbench modules for initial verification of RTL designs, achieving an 85% success rate and accelerating early-stage validation.
Supported cross-functional debug by addressing verification engineer queries and resolving RTL issues, ensuring faster turnaround and stronger design-verify collaboration.
Gained critical exposure to end-to-end ASIC design and verification workflows, sharpening my RTL design expertise and laying the groundwork for my career in the Semiconductor Industry.

RTL DesignRTL Verification

Intel corporation

Pre-Si Design QnR Intern

Aug 2022 – Dec 2022 · 4 mos · Bengaluru, Karnataka, India · Hybrid

Evaluated critical circuits for synchronization failures using Intel’s specialized tools, mitigating risks and preventing ~40% of potential high-impact failures before tape-out.
Reconfigured and optimized 4 RTL circuits with a precision rate of 65%, significantly improving synchronization robustness and design stability.
Leveraged Cadence expertise to streamline design analysis workflows and proactively identify optimization opportunities.
Developed an early understanding of how design decisions directly shape reliability, building a foundation for system-level thinking in semiconductor verification.

RTL VerificationCadence Virtuoso

Noida metro rail corporation limited

Summer Intern

May 2020 – Jun 2020 · 1 mo · Noida, Uttar Pradesh, India · Remote

Designed a real-time body temperature screening system for metro entry points, to shape a cost-effective and scalable deployment plan. While the work remained at the stage of research and simulation, reviewed by an NMRC officer, it gave me early exposure to framing problems under real-world constraints, balancing accuracy, throughput, and feasibility, at an early stage in my engineering journey.

Research