Sachin Mirashe — Software Engineer
• Physical Implementation at RV-VLSI Design Center. • Understanding & knowledge of Deep Sub-Micron Fabrication Process. • Understanding & Knowledge of CMOS & Circuit Theory. • Good Knowledge of Digital Design Concepts • Good in Verilog & Writing Synthesis friendly RTL • Moderate Hands-on Experience of each phase of RTL-GDSII flow • Understanding & knowledge of STA, Statistical STA & Timing Models • Timing Closure on DSM Technology • Aggressive Timing & Area Budgeting. • Power Integrity check through IC Compiler (IR Drop Analysis) • Understanding & knowledge of Low Power Technique • Knowledge of DFM Techniques. • Basic understanding of DFT (Scan insertion ,Boundary Scan, Built In Self Test ) • Basic Tcl Scripting
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Timing Analysis.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 10 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in Physical Design and Timing Closure.
- Proficient in Low Power Techniques and Static Timing Analysis.
- Hands-on experience with RTL-GDSII flow and DFM Techniques.
Work Experience
Intel Corporation
Physical Design Engineer (5 yrs 7 mos)
Laksh Semiconductors
Physical Design Engineer (2 yrs 2 mos)
Graphene Semiconductors
Physical Design Engineer (1 yr 1 mo)
Education
Advanced Diploma in ASIC Design at RV-VLSI Design Center
B.E
H.S.C at Aurangabad Board
SSC at Latur Board
