Jigar Pankhania

Product Engineer

Bengaluru, Karnataka, India7 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI design and digital circuit development.
Proven track record in performance verification and physical design.
Strong foundation in telecommunications and research methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and digital circuit design.

Contact

Skills

Core Skills

Digital Circuit DesignVery-large-scale Integration (vlsi)Physical DesignPerformance Verification

Other Skills

VerilogAnalog Circuit DesignTelecommunicationsResearchCadence VirtuosoModelSimAltera QuartusStatic Timing AnalysisFloorplanPlacementGlobal ClockingRoutingFormal Equivalence VerificationPhysical VerificationDRC Checks

Experience

7 yrs 8 mos

Total Experience

2 yrs 6 mos

Average Tenure

4 yrs 4 mos

Current Experience

Intel corporation

Product Development Engineer

Dec 2021 – Present · 4 yrs 4 mos · Bengaluru, Karnataka, India

Digital Circuit DesignVerilogPhysical DesignAnalog Circuit DesignVery-Large-Scale Integration (VLSI)Telecommunications+6

Globalfoundries

Sr. Engineer Integration & Yield

Jul 2019 – Dec 2021 · 2 yrs 5 mos · Bangalore

Intel corporation

Graduate Technical Intern

Jul 2018 – Jun 2019 · 11 mos · Bangaon Area, India

 Floorplan, Placement, Global Clocking, Routing
Minimize the total chip area, Voltage areas, Hierarchical floorplan, Placement Bounds, Placement
Blockages, Timing driven placement
 Dealt with many type of congestions
Global Route Congestion, Channel Congestion, Cell Density, Pin Density
 Performance Verification
Cleaning timing violations STA
Checked and fixed setup as well hold violations at the all corners present in the design.
 Formal Equivalence Verification
RTL to Netlist
 Physical Verification: DRC Checks