Dhanalakshmi Renganathan

Software Engineer

Kottayam, Kerala, India7 yrs 8 mos experience
Highly Stable

Key Highlights

  • 7 years of RTL design experience with Verilog and VHDL.
  • Expertise in 5G Low Phy and Video Protocol design.
  • Proficient in hardware testing and design verification.
Stackforce AI infers this person is a skilled RTL Design Engineer with expertise in telecommunications and video protocols.

Contact

LinkedIn

Skills

Other Skills

RTL DesignStatic Timing AnalysisSimulationsDebuggingRadio Frequency (RF)Field-Programmable Gate Arrays (FPGA)System on a Chip (SoC)GitXilinx VivadoWindowsLinuxImplementationDigital Signal Processing on FPGADigital Image Processing on FPGABoolean Algebra

About

7 Years of experience in RTL design using Verilog, System verilog and VHDL Experienced in Video Protocol design, 5G Low Phy design, High speed SERDES, DisplayPort, DSP, ISP, Video codec, Coaxpress Protocos, Block floating point compression and decompression, IP/SoC design, Quality checks - Lint, CDC and RDC , UPF, Top Integration, Synthesis, Functional and Timing simulations, Hardware Testing, 5G NR , LTE L1,MATLAB, Design Verification

Experience

7 yrs 8 mos
Total Experience
2 yrs 4 mos
Average Tenure
8 mos
Current Experience

Amd

MTS Silicon Design Engineer

Sep 2025 – Present · 8 mos · Bengaluru, Karnataka, India

Intel corporation

ASIC Design Engineer

Apr 2022 – Sep 2025 · 3 yrs 5 mos · Bengaluru, Karnataka, India

Ignitarium

Senior Design Engineer

Aug 2021 – Apr 2022 · 8 mos · Kochi, Kerala, India

Vvdn technologies

2 roles

Senior RTL Design Engineer

Promoted

Oct 2020 – Jul 2021 · 9 mos · Kochi, Kerala, India

RTL Design Engineer

Jul 2018 – Sep 2020 · 2 yrs 2 mos · Kochi, Kerala, India

Education

Rajiv Gandhi Institute of Technology, Kottayam

Master of Technology - MTech

Jan 2016 – Jan 2018

Government Engineering College Idukki - India

Bachelor of Technology - BTech

Jan 2012 – Jan 2016

MT Seminary HSS Kottayam

Science

Jan 2010 – Jan 2012

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