Rahul Vishal — CTO

As the Director of ASIC Design at Alphawave IP Group, I lead a team of seasoned professionals for an end-to-end ASIC development, from RTL to GDS2. I have over 23 years of industry experience in different domains of physical design, with a strong focus on Static Timing Analysis (STA), physical design, DFT and power optimization. I have successfully taped out half-reticle chip in N7 node, plus couple of other chips in my role Director - ASIC design. I have a Master of Engineering in Microelectronics from Birla Institute of Technology and Science, Pilani, and a Bachelor of Engineering in Electronics and Communication from MVJ College of Engineering. I also have three certifications from LinkedIn and Synopsys Inc that enhance my skills in signoff extraction, working with high-conflict people, and speaking up at work. I am proficient in TCL, EDA, VLSI, scripting, and constraints screening. My mission is to deliver high-performance connectivity solutions for data markets that meet the highest standards of quality and reliability.

Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in ASIC design and physical design.

Location: Bengaluru, Karnataka, India

Experience: 23 yrs 4 mos