Satheesh Kumar

Software Engineer

Bengaluru, Karnataka, India14 yrs 6 mos experience

Key Highlights

14+ years in VLSI verification expertise.
Specialized in power management verification for server-grade SoCs.
Proven track record in architecting constrained random test benches.

Stackforce AI infers this person is a Semiconductor and Networking verification expert with extensive experience in power management and SoC design.

Contact

Skills

Core Skills

Design VerificationSystem On A Chip (soc)

Other Skills

Test Bench ArchitectureSystemVerilogUVMUniversal Verification Methodology (UVM)IP verificationPower estimationC (Programming Language)Test PlanningCPU Power characterizationLow power DVRTL verificationRTL designVerilogVMMAMBA AHB

About

Principal DV Engineer with 14+ years in VLSI verification, specializing in Architecting Constrained Random Test benches and verifying complex SoCs/IPs across Data Center, Networking, and SmartNIC domains. Proven expertise in power management verification for server-grade SoCs and custom ARM CPUs, including Snapdragon® X Elite. Skilled in SystemVerilog, UVM, and advanced verification methodologies, with a track record of delivering robust, high-performance silicon solutions.

Experience

14 yrs 6 mos

Total Experience

3 yrs 1 mo

Average Tenure

2 yrs 2 mos

Current Experience

Microsoft

2 roles

Principal DV Engineer

Promoted

Mar 2026 – Present · 1 mo · Bengaluru · Hybrid

Cloud

Test Bench ArchitectureSystemVerilogUVMDesign verificationSystem on a Chip (SoC)

Senior DV Engineer

Jan 2024 – Feb 2026 · 2 yrs 1 mo · Bengaluru · Hybrid

Cloud + AI

Universal Verification Methodology (UVM)IP verificationDesign verification

Qualcomm

2 roles

Senior Staff Engineer

Promoted

Nov 2022 – Jan 2024 · 1 yr 2 mos

Development of power benchmarking tests for the custom ARM CPU (Oryon) core
Characterization of Power estimation and Limit management for the Oryon CPU cluster at the RTL level.

UVMSystem on a Chip (SoC)Design verification

Staff Engineer

Mar 2021 – Nov 2022 · 1 yr 8 mos

Design verification for various Power Management IPs, including Digital Power Estimation and Limit Management, Temperature HUB, and PMIC Controller, as part of the Server SoC development. Additionally, performing SoC level verification for Power Management workflows within the Server SoC.

C (Programming Language)UVMDesign verification

Nuvia inc

Member Of Technical Staff

Oct 2020 – Mar 2021 · 5 mos · Bengaluru, Karnataka, India

NUVIA Inc. is now part of Qualcomm, following the acquisition in March 2021
Design Verification of the Multiple Power Management IP's for the Server SoC

IP verificationC (Programming Language)Design verification

Broadcom limited

2 roles

R&D Engineer IC Design 3

Nov 2017 – Oct 2020 · 2 yrs 11 mos

IP level verification of the high-speed, software-defined DMA subsystem with 16 flows/ring for the 100G Data Centre accelerator SoC (SmartNIC).
SoC level integration verification of the Video Decoder, supporting resolutions from 320p to 4K, for the Data Centre accelerator SoC (Video Transcoder)

C (Programming Language)UVMDesign verification

R&D Engineer IC Design 2

Nov 2015 – Oct 2017 · 1 yr 11 mos

IP level verification for the inline QoS scheduler tailored for the Next Gen 33G/16 Port Router Switch.
Subsystem verification for the audio subsystem, featuring Dolby Atmos support for the upcoming generation of VoIP & Wireless Audio SoC
SoC Level Integration and Verification of Audio subsystem for VoIP & Wireless Audio SoC

IP verificationC (Programming Language)Design verification