Anuj Grover

Head of Design

South Delhi, Delhi, India25 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in Memory Design and Architecture.
  • Strong background in RnD collaborations and prototyping.
  • Experienced educator and mentor in engineering.
Stackforce AI infers this person is a Semiconductor Design Expert with a focus on Memory Solutions and Education.

Contact

Skills

Core Skills

Memory DesignProject Management

Other Skills

Circuit designDesign AnalysisDFMEADebugDesign ArchitecturesCreativity and InnovationInventive Problem SolvingSRAMCircuit AnalysisAnalogCoaching & MentoringPeople DevelopmentFacilitationUniversity TeachingCreativity Skills

About

I joined STMicroelectronics as a project trainee with Memory Design team in 1999. I enjoyed the experience so much that I decided to join the same group as a designer as soon as I completed my graduation at IIT Delhi. At IIT Delhi, I got to work closely with Prof. S.D. Joshi, Prof. J.K. Chatterjee and many others. My B.Tech Project was with Prof. Subrat Kar on SDH/SONET switches by Transwitch. After working for about 2yrs 3months, I pursued higher technical education at University of California, San Diego towards a Masters in Science Degree. At UCSD, I worked with Prof. Andrew Kahng on reliability metric and Prof. Yuan Taur on device design. I joined La Jolla Advanced Design Center of STMicroelectronics to work on a project of Scalable Memory Architectures with Thomas Zounes. I returned to join STMicroelectronics at NOIDA to work on Memory Design. Currently, I am involved in embedded memory design and related solutions design in UTBB FDSOI at 28nm. I am also responsible for facilitating RnD relationships with partners and universities to explore relevant future solutions related to SRAM subsystems. Through all these years, I have also been involved in activities related to Community Service through various avenues at ST. I am currently the convener of SMILES - Smart Minds Influencing Life and Earth Sustainably - at ST Greater NOIDA Specialties: Memory (SRAM/ ROM) Design - Architecture, Circuit, Verification, Silicon Qualification etc. Trainer - "From Creativity to Innovation"; "Science and Technology" Non-profits Mentoring / Coaching subordinates

Experience

25 yrs 10 mos
Total Experience
18 yrs 8 mos
Average Tenure
12 yrs 11 mos
Current Experience

Indraprastha institute of information technology, delhi

5 roles

Head, Centre for Intelligent Product Development (CiPD)

Promoted

Nov 2023Present · 2 yrs 5 mos

Associate Dean - IRD

Jul 2021Sep 2023 · 2 yrs 2 mos

Chairman, Institute Innovation Council

Jun 2021Oct 2023 · 2 yrs 4 mos

Associate Professor

Promoted

Feb 2019Present · 7 yrs 2 mos

Guest Faculty

May 2013Feb 2019 · 5 yrs 9 mos

Stmicroelectronics

3 roles

Trainee

May 2003Dec 2003 · 7 mos

  • I worked on scalable memory architecture design by using domino logic with Tommy Zounes as a part of project towards completion of MS degree.

Principal Engineer

Jun 2000Feb 2019 · 18 yrs 8 mos

  • My role has augmented over the past years and responsibilities and experience keeps adding on. I am presently responsible for RnD prototyping, RnD collaborations and Knowledge Enhancement related activities for Static Memory Design team at STMicroelectronics.
  • The technical skills of Circuit design, Design Analysis, DFMEA, Debug, Design Architectures, Project Management etc. come in handy on a regular basis.
  • I am expected to collaborate, share, synergize, anticipate, forge networks and build healthy professional relationships in the present role.
  • I am also a trainer for in-house training "From Creativity to Innovation" and continuously work at ST-India level to continuously add to the experience of all colleagues at ST-India, through various internal forums.
Circuit designDesign AnalysisDFMEADebugDesign ArchitecturesProject Management+1

Trainee

May 1999Jul 1999 · 2 mos · NOIDA

  • Trainee in SRAM/ ROM design group

Education

Massachusetts Institute of Technology

Diploma — Theory of Inventive Problem Solving

Jan 2018Jan 2018

Tufts University

Certification — TRIZ for Product Development Strategies

Jan 2018Jan 2018

Indian Institute of Technology, Delhi

PhD — Electrical Engineering

Jan 2010Jan 2015

UC San Diego

MS — Electronic Circuits and Systems

Jan 2002Jan 2003

Indian Institute of Technology, Delhi

B.Tech — Electrical Engineering

Jan 1996Jan 2000

Mata Jai Kaur Public School

Schooling

Jan 1988Jan 1996

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